1. Computer Organization and ASSEMBLY LANGUAGE
Lecture 23 & 24
Instruction Cycle
Instruction Pipelining
Course Instructor: Engr. Aisha Danish

2. Instruction Cycle
Revision
Stallings Chapter 3 35

3. Instruction Cycle
Fetch: Read the next instruction from memory into the processor.
Execute: Interpret the opcode and perform the indicated operation.
Interrupt: If interrupts are enabled and an interrupt has occurred, save the current process state and service the interrupt

4. The Indirect Cycle
The execution of an instruction may involve one or more operands in memory, each of which requires a memory access
Further, if indirect addressing is used, then additional memory accesses are required
We can think of the fetching of indirect addresses as one more instruction stages
As shown in Figure 12.4, the main line of activity consists of alternating instruction fetch and instruction execution activities
After an instruction is fetched, it is examined to determine if any indirect addressing is involved
If so, the required operands are fetched using indirect addressing
Following execution, an interrupt may be processed before the next instruction fetch.

5. Instruction Cycle with Indirect

6. Instruction Cycle State Diagram

7. The Indirect Cycle May require memory access to fetch operands
Indirect addressing requires more memory accesses
Can be thought of as additional instruction subcycle

8. Data Flow (Instruction Fetch)
Depends on CPU design
In general:
Fetch
PC contains address of next instruction
Address moved to MAR
Address placed on address bus
Control unit requests memory read
Result placed on data bus, copied to MBR, then to IR
Meanwhile PC incremented by 1

9. Data Flow (Data Fetch) IR is examined
If indirect addressing, indirect cycle is performed
Right most N bits of MBR transferred to MAR
Control unit requests memory read
Result (address of operand) moved to MBR

10. Data Flow (Fetch Diagram)

11. Data Flow (Indirect Diagram)

12. Data Flow (Execute) May take many forms
Depends on instruction being executed
May include
Memory read/write
Input/Output
Register transfers
ALU operations

13. Data Flow (Interrupt) Simple Predictable
Current PC saved to allow resumption after interrupt
Contents of PC copied to MBR
Special memory location (e.g. stack pointer) loaded to MAR
MBR written to memory
PC loaded with address of interrupt handling routine
Next instruction (first of interrupt handler) can be fetched

14. Data Flow (Interrupt Diagram)

15. Prefetch Fetch accessing main memory
Execution usually does not access main memory
Can fetch next instruction during execution of current instruction
Called instruction prefetch 36

16. Improved Performance But not doubled:
Fetch usually shorter than execution
Prefetch more than one instruction?
Any jump or branch means that prefetched instructions are not the required instructions
Add more stages to improve performance 37

17. Pipelining Fetch instruction Decode instruction
Calculate operands (i.e. EAs)
Fetch operands
Execute instructions
Write result
Overlap these operations 38

18. Two Stage Instruction Pipeline

19. Timing Diagram for Instruction Pipeline Operation39

20. The Effect of a Conditional Branch on Instruction Pipeline Operation40

21. Six Stage Instruction Pipeline