1. High Level Synthesis Overview
John Curreri
Seth Koehler

2. Outline Introduction Impulse C Tool demonstration High Level Synthesis
Computational parallelism
Types of communication
Communication Library
Design Flow
Tool demonstration

3. High Level Synthesis Translates C code to HDL Built-in communication
Higher level of abstraction
Usually a subset of ANSI C
No pointers
No ANSI C libraries for FPGA
HDL is generated as a project file for Xilinx or Altera tools
Built-in communication
Separate C source files are made for the CPU & FPGA
Similar communication function calls between CPU & FPGA

4. High Level Synthesis (continued)
Computational parallelism
Pipelining of loops
for(), while(), etc.
Use of library functions
HDL coded functions called at HLL
FFT, Floating point operations
Replication of functions defined in hardware
Types of communication
DMA transfers
Efficient transfer of large chucks of data
Stream transfers
Steady flow of data
Buffered for transfer rate changes

5. Impulse C Communication Library
co_memory
Large transfer size - DMA
From CPU array to SRAM
From SRAM to FPGA block RAM
co_stream
Small transfer size - FIFO buffered
FIFO is implemented in block RAM on FPGA
co_register
Small transfer size - unbuffered
Synchronization
co_signal
Single process to process
One process waits for another to signal it to continue
co_semaphore
Multiple processes to processes
GOALS
Accelerate the process of improving performance (end of development cycle)
MOTIVATIONS
RC systems are even more complex than traditional parallel programs
Manually inserting code to monitor code takes time, many iterations, is error prone
CHALLENGES
What does performance analysis in RC even mean? How do related software concepts translate?

6. Design Flow
GOALS
Accelerate the process of improving performance (end of development cycle)
MOTIVATIONS
RC systems are even more complex than traditional parallel programs
Manually inserting code to monitor code takes time, many iterations, is error prone
CHALLENGES
What does performance analysis in RC even mean? How do related software concepts translate?

7. DEMO
GOALS
Accelerate the process of improving performance (end of development cycle)
MOTIVATIONS
RC systems are even more complex than traditional parallel programs
Manually inserting code to monitor code takes time, many iterations, is error prone
CHALLENGES
What does performance analysis in RC even mean? How do related software concepts translate?