1. Pattern Compression for Multiple Fault Models
- Priyadharshini S

2. Outline Introduction Fault modeling Fault models
Multiple fault modeling
Pattern compression
Motivation
Existing technique
N-Model Tests using ILP
Problem statement
Implementation
Results
Proposed technique
8/26/2009
VLSI Design and Test Seminar

3. Introduction
Fault modeling
Physical defects during manufacturing are modeled as physical parameters
E.g. Line stuck at 0, line stuck at 1, delay at output of gate
VDD
=> o/p stuck at 0
i/p
o/p
GND 3
8/26/2009
VLSI Design and Test Seminar

4. Introduction Fault models Stuck-at Transition Path Delay IDDQ 4
Transistor shorts and opens
Stuck-at-0 and stuck-at-1 faults
Transition
Timing defects lumped at the output of gates
Slow to rise and slow to fall faults
Path Delay
Timing defect due to cumulative propagation delay of a combinational path
IDDQ
Defective chip identified by examining current drawn from power supply 4
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VLSI Design and Test Seminar

5. Introduction (Fault models.. Continued)
Static Bridging
Shorts between groups of signals
1-dominant (OR bridge) and 0-dominant (AND bridge)
Combinational
Dynamic Bridging
Feedback bridging fault
Can produce memory states in otherwise combinational logic 1 1 1
0-dominant (AND bridge)
1-dominant (OR bridge) 5
8/26/2009
VLSI Design and Test Seminar

6. Introduction Importance of multiple fault modeling
Each fault model targets specific defects
To detect most faults, more fault models must be considered
Number of fault models that need to be considered is increasing with increasing process complexity
leads to an increase in the volume of test vectors
increases memory requirement and test time on tester 6
8/26/2009
VLSI Design and Test Seminar

7. Introduction Pattern compression
Elimination of test patterns without affecting test coverages
Scope for compression
Existence of pattern sets that cover all and more faults, than covered by a different pattern set
f1, p1
f2, p2
Fault universe 7
8/26/2009
VLSI Design and Test Seminar

8. Motivation Test generation for multiple fault models
Combine pattern sets covering different fault models
Concatenating pattern sets - number of vectors grows rapidly
Pattern set of one fault model may detect faults of a different fault model f1 f2 p1
Fault
coverage
Number of patterns 8
8/26/2009
VLSI Design and Test Seminar

9. Existing Technique Test patterns generated for one fault model
Generated pattern set simulated against faults of a different fault model
Test patterns generated for undetected faults
Repeated till test patterns are generated for all fault models f1
p1 ,f2 p1
Fault
coverage
Number of patterns p2 p3
(p1 + p2),f3
Total number of patterns = p1 + p2 + p3 f2 f3 9
8/26/2009
VLSI Design and Test Seminar

10. Existing Technique Fault model ordering effects number of patterns
Optimized test pattern set cannot be found unless all possible orders have been considered
Number of possible ways to order models = n!
n is number of fault models FC f1 f2 p1 p2 f2 FC f1 p4 p3
p1 + p2 ≠ p3 + p4 10
8/26/2009
VLSI Design and Test Seminar

11. N-Model Tests using ILP
Minimization problem
Obtain minimized test set for considered fault models
Take advantage of vectors detecting faults in multiple fault models
Circuit
Type of vecs
Mentor Fastscan vectors
Fault Cov. (%)
Un-minimized
Minimized
c3540
Stuck-at
167
130
96.00
IDDQ(pseudo stuck-at) 53 45
99.09
Transition delay
299
229
96.55
Total
519
404 -
s5378
150
145
99.30 71 70
85.75
Transition delay (LOS)
319
293
98.31
Transition delay (LOC)
256
242
90.05
796
750 - 
N-Model Tests for VLSI Circuits, Nitin Yogi and Vishwani D. Agrawal,
40th Southeastern Symposium on System Theory 11
8/26/2009
VLSI Design and Test Seminar

12. N-Model Tests using ILP
Obtain fault dictionary by fault simulations (without fault dropping)
Determine faults detected by each vector
‘F’ faults : for all considered fault models
‘N’ vectors : generated for all considered fault models
Test minimization by Integer Linear Program (ILP)
Set of integer variables
Set of constraints
Objective function 12
8/26/2009
VLSI Design and Test Seminar

13. N-Model Tests using ILP
Define [0, 1] integer variable:
tj – for each vector ; j = 1 to N
tj = 0 : drop vector j
tj = 1 : select vector j
Constraints {ck} for kth fault, k = 1 to F
For kth fault detected by vectors u, v and w ck : tu + tv + tw ≥ 1
Objective function
Minimize ∑ tj
N : total number of vectors
tj : variables to select vectors N
j = 1 13
8/26/2009
VLSI Design and Test Seminar

14. N-Model Tests using ILP
Example
Objective function
Minimize t1 + t2 + t3
Constraints
t2 + t3 ≥ 1
t1 ≥ 1
t1 + t3 ≥ 1 f1 f2 f3 v1 √ v2 v3 14
8/26/2009
VLSI Design and Test Seminar

15. N-Model Tests using ILP
Results
Ckt.
Number of ATPG vectors
Number of
Vectors using ILP
% reduction
c3540
404
225
44.31
s5378
750
320
57.33 15
8/26/2009
VLSI Design and Test Seminar

16. Proposed Technique Problem statement
Dynamic compression of patterns without affecting test coverages
Variation in slopes of fault simulation curves is utilized
Some patterns of a particular fault model may have high detection capability while others may not
Pf1 , f2
Pf1 , f3
Pf2 , f3
Pf2 , f1
Pf3 , f1
Pf3 , f2 FC
Pa , b: Simulation of pattern set of fault model
A against faults of fault model b
Number of patterns 16
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VLSI Design and Test Seminar

17. Proposed Technique Number of patterns saved f1 f2 Pf2 , f1 FC Pf1 , f2
Defined for a pattern set
It is the number of patterns that would be generated by other fault model ATPGs to detect the same faults as detected by the pattern set under consideration f1
Pf2 , f1 f2
Pf1 , f2
Pf2’
Pf1’ FC
Number of patterns saved by Pf1 = Pf1’
Number of patterns saved by Pf2 = Pf2’ 17
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VLSI Design and Test Seminar

18. Proposed Technique Patterns generated in blocks
A block is a set of fixed number of patterns
Start with entire fault set for all fault models
Generate a fixed number of patterns individually for each of the N fault models
Simulate the N pattern sets against the faults of the remaining N-1 fault models
Find the number of patterns saved by each pattern set f1 f2 f3 15 21 30 5 12 8
= 36
= 35
= 20 18
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VLSI Design and Test Seminar

19. Proposed Technique
The pattern set with maximum fault savings is chosen
Pattern set of fault model 1 chosen in example shown
Pattern set stored
Undetected faults information is updated for all fault models
Repeat the process until required fault coverage is reached in every fault model
Undetected faults become the new targeted faults
Pattern generation and simulation abandoned for a fault model once required coverage is reached for that fault model 19
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VLSI Design and Test Seminar

20. Proposed Technique Results About 30% reduction in number of patterns
Tool used: Synopsys TetraMAX
About 30% reduction in number of patterns
With respect to existing technique
With 2 fault models: stuck, transition
Test coverages: around 90% for transition and 95% for stuck-at
Tested with upto a total of 5 fault models
Run-time
in the order of a few days for a circuit with 2 million stuck-at faults 20
8/26/2009
VLSI Design and Test Seminar

21. Proposed Technique Challenges Run – time optimization
Modeling combinational faults like stuck-at to be compatible with other fault models
Future work
Reverse simulation
Post-pattern generation optimization
N-Model Tests using ILP
Adaptive block size variation 21
8/26/2009
VLSI Design and Test Seminar

22. THANK YOU