1. BIPOLAR INTEGRATED CIRCUIT FABRICATION
ZhongTenghui

2. 1. Introduction
2. Buried layer and epitaxy
3. Isolation

3. 1.Introduction
The design of bipolar transistor is intimately interwoven with the methods used for fabrication. Any study of bipolar transistors would therefore be incomplete without consideration of the limitations imposed by the fabrication technology. Bipolar transistor are also generally incorporated into integrated circuits, and hence the transistor designer must also be aware of the restrictions imposed by the circuit configuration. In high-speed digital circuits these restrictions can be distilled into the requirement to minimize all parasitic resistances and capacitances. For analogue circuits the requirements are more subtle, and a close interaction between the circuit and process designer is needed to extract optimum performance from the product.

4. The design procedure at its most fundamental is the management of engineering trade-offs, and it is essential that these are dictated by the particular application. In this context the most important trade-offs are those between speed and breakdown voltage and between analogue and digital capability. High breakdown voltage imply the use of a thick , lowly doped epitaxial layer in order to give a wide collector/base depletion region. Similarly, deep junctions are implied in order to prevent premature breakdown around the periphery of the device. These requirements run counter to those for speed, where shallow junctions are needed to minimize peripheral capacitance and thin, heavily doped epitaxial layer to suppress charge storage and base-widening effects. For analogue applications good matching between devices is of primary importance. In addition, many analogue circuits require both npn and pnp transistors to be available, as well as high-quality resistors and capacitors. Although these requirements do not run directly counter to those of a good digital process, it is often difficult to achieve the ultimate in switching speed while maintaining reproducibility of transistor and component characteristics.

5. From the preceding brief consideration of the trade-offs involved in the bipolar device and process design it is not surprising to discover that a wide variety of fabrication processes are currently used in industry. In this chapter we will attempt to extract the key elements of these processes and hence compile a set of bipolar process building blocks. Common yield problem associated with troubleshooting outlined.
Emitter and base regions are clearly needed for the transistor itself as well as additional regions to make the transistor suitable for use in integrated circuits. In particular , some form of electrical isolation must be included to prevent unwanted conduction between adjacent transistors. A buried layer is desirable to reduce the collector resistance, and this necessitates the use of an epitaxial layer. Finally, a low-resistance metallization system is needed for interconnections and for making ohmic contacts to the transistor. These are the key elements of any bipolar process, and will be considered in more detail in the following sections.

6. Emitter and base regions are clearly needed for the transistor itself as well as additional regions to make the transistor suitable for use in integrated circuits. In particular , some form of electrical isolation must be included to prevent unwanted conduction between adjacent transistors. A buried layer is desirable to reduce the collector resistance, and this necessitates the use of an epitaxial layer. Finally, a low-resistance metallization system is needed for interconnections and for making ohmic contacts to the transistor. These are the key elements of any bipolar process, and will be considered in more detail in the following sections.

7. 2.BURIED LAYER AND EPITAXY
The relatively low loping concentration in the collector of a bipolar transistor(typically )introduces a large collector series resistance. This can seriously degrade the electrical performance of the transistor, giving rise to a serious reduction in the current-carrying capability of the transistor and an increase in the saturation voltage. For these reasons, a buried layer is incorporated below the active device region. This provides a low-resistance path to the collector contact, thereby short-circuiting the highly resistive epitaxial collector. In some cases, an collector diffusion, connecting the collector contact and the buried layer, is also included to further reduce the collector resistance.

8. The buried layer is fabricated by implanting arsenic or antimony and then diffusing the relevant dopant into the substrate in a high temperature. These dopants are chosen over phosphorus because of their very low diffusion coefficient in silicon. A dry oxygen ambient is generally chosen for drive-in in order to produce a step in the silicon surface(Figure 6.1b) for later alignment to the buried layer. This step comes about because the oxidation rate of heavily doped silicon is much higher than that of lightly doped silicon. As a result, more silicon is consumed over the buried layer, giving rise to a small depression, as illustrated in Figure 6.1. The buried layer junction depth is determined by the requirements for a low sheet resistance (typically /sq or less) to minimize collector resistance, and a low surface concentration to avoid autodoping during epitaxy. Sheet resistances lower than about /sq are difficult to achieve because of defect generation during drive-in and epitaxial growth.

10. Epitaxy is the term applied to the growth of a single-crystal layer of semiconductor on a single-crystal substrate. The crystalline substrate serves a seed of the epitaxial growth, and allows the process to take place at a temperature well below the melting point of silicon. Temperatures of are typically used, the lower temperatures being advantageous for thinner epitaxial layers. The epitaxial process proceeds by the reduction of a gaseous silicon compound such as silane ( ),dichlorosilane( )or silicon tetrachloride( ). Dopants can be incorporated into the growing epitaxial layer by mixing the silicon source gas with gaseous hydride ( , ,or ) . The selection of the optimum conditions for epitaxial growth is very complex decision, based on factors such as reactor configuration, deposition temperature, growth rate, surface cleanliness, etc. The crystalline quality of epitaxial layers is of paramount importance, and is generally worse than that of the original substrate. Defects such as dislocations are able to propagate from the substrate into the growing epitaxial film, and additional defects such as epitaxial stacking faults are often nucleated at impurities and damage on the substrate surface.

11. Epitaxial layer thickness can be controlled over a wide range of values. At the upper limit layers several hundred micron thick are routinely grown for power device application, and at the lower limit layers of less than a micron are grown for high-speed digital applications. In sub-micron epitaxial layers autodoping and out-diffusion of the buried layerare the main factors that constrain the extent that the thickness can be reduced. This latter mechanism is illustrated in Figure 6.1(c), where it can be seen as the diffusion of the buried layer dopant up into the epitaxial layer. The epitaxial doping concentration can be varied from approximately down to . There low values of doping are only achievable if the reactor is thoroughly cleaned prior to deposition. Autodoping from the rear of the wafer can be a problem, but sealing the rear surface with an oxide or nitride layer is effective in reducing this effect. In bipolar processes the epitaxial layer doping is generally determined by the requirement to suppress base-widening effects as described in Chapter 3. Epitaxial doping concentrations around are typical.

12. Autodoping of epitaxial layers occurs through solid state diffusion and evaporation of dopant from the substrate. The dopant is then incorporated into the growing epitaxial layer through the gas phase. This is a particular problem in bipolar processes because of the presence of the heavily doped buried layer. Its main electrical effect is an increase in the collector/base capacitance of the transistor. The epitaxial layer thickness also has to be greater than strictly necessary in order to prevent the dopant from reaching the collector junction. Autodoping can be minimized by ensuring that the buried layer surface concentration is low and by growing the epitaxial layer at a low temperature. Unwanted dopant is also in corporated into the epitaxial layer by out-diffusion from the buried layer through the interface. This is illustrated in the schematic doping profile in the figure 6.2. diffusion from the buried layer gives rise to an approximately gaussian profile, whereas autodoping from the gas phase gives a tail at low doping concentrations .

14. Pattern shift and pattern distortion or washout are also often observed in bipolar process.

15. Considerable advances have recently been made in techniques for selectively depositing epitaxial. An example of selective epitaxy is given in Figure 6.4, where it can be seen that the silicon is deposited only in those areas where the substrate is exposed to the surface. The major problem with selective epitaxy are the formation of defects and facets around the periphery of the epitaxial regions. These facets are illustrated in Figure 6.4, and prevent the window from being completely filled with silicon. Experiments have shown that facet formation can be suppressed by coating the sidewall of the silicon dioxide with polysilicon.

16. 3.ISOLATION The simplest method of isolation for bipolar circuit is junction isolation. Electrical isolation between transistors or components in adjacent n-epitaxial island is achieved by reverse biasing the collector/isolation pn junction.
双极电路的隔离最简单的方法是结隔离。通过集电极/pn结隔离层的反向偏置实现晶体管之间或相邻N -外延岛组件之间的电隔离。
三层扩散双极型晶体管截面图

17. Oxide isolation is by far the most popular method of isolation for bipolar integrated circuit.
氧化物隔离是目前双极集成电路最流行的隔离方法。

18. A typical fabrication sequence for oxide isolation is illustrated in Figure 6.7
典型的介质氧化隔离程序 防腐蚀涂层 氮化硅 氧化物垫层

20. THANKS