1. Lab6 HW/SW System Debug Lab : MicroBlaze

2. Objectives Add ChipScope Analyzers into a system. System Debugging.
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3. Procedure
This lab comprises several steps involving simulation. Below each general instruction for a given procedure, you will find accompanying step-by-step directions and illustrated figures providing more detail for performing the general instruction.
If you feel confident about a specific instruction, feel free to skip the step-by-step directions and move on to the next general instruction in the procedure.
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4. Opening the Project
Create a lab6 folder in the X:\EDKLab\ directory. If you wish to continue with your completed design from lab5 then copy the contents of the lab5 folder into the lab6 folder. 1. 2. 3. 4.
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5. Opening the Project
Open XPS, click File → Open Project and browse to the project which is in the directory: X:\EDKLab\lab6, then click system.xmp to open the project. 1. 2.
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6. Compiler Optimization
Using Project  Software Platform Settings … open the Software Platform Settings GUI.
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7. Compiler Optimization
Click on the Processor, Driver Parameters and Interrupt Handlers tab.
Delete the timer_int_handler in the Current Value field so the field is blank. Click 確定. 1. 2. 3.
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8. Compiler Optimization
Copy the system_delay.c file to the current project X:\EDKLab\Lab6\code.
Remove system_timer.c from the MyProj project and add the new file system_delay.c. 1. 4. 5. 2. 3. 6.
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9. Compiler Optimization1.
Set the compiler optimization level to No Optimization by double clicking on the MyProj title and selecting the Optimization Tab as shown in following figure, and select the option to Create symbols for debugging as shown. Click 確定. 2. 3. 4.
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10. Compiler Optimization
Select Download so the sources are recompiled and loaded to the board. The 7segments should display the counter running at 0.1 seconds.
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11. Compiler Optimization
Set the compiler optimization level to Level 2 and download the project again.
Notice the difference in speed of display increment due to compiler optimizations. 1. 2.
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12. ChipScope Core Instantiation
ChipScope Core Connections
OPB/IBA Core
CS_ICON_Control
SYS_RST
Mb_halt
(MicroBlaze)
Dbg_stop
(MicroBlaze)
iba_trig_in
iba_trig_out
Sys_clk_s
OPB_CLK
ICON Core
Control
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13. ChipScope Core Instantiation
Click Project  Add Cores (dialog).
In the Peripherals tab, add the chipscope_icon and chipscope_opb_iba peripherals. 2. 3. 1. 4.
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14. ChipScope Core Instantiation1.
In the Bus connection tab, connect the chipscope_opb_iba as a BA (bus analyzer) device to the OPB bus.
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15. ChipScope Core Instantiation
In the Ports tab, connect the chipscope_cores as shown in following Figure.
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16. ChipScope Core Instantiation
In the Parameters tab, configure the chipscope_cores. Select C_SYSTEM_CONTAINS_MDM and << ADD parameter to the list.
Set this value to 1 - This parameter indicates whether the system containing the ChipScope Icon core contains the OPB MDM peripheral or not. The opb_mdm debug module is used for communication between MicroBlaze and the Xilinx.Microprocessor Debugger (XMD) interface. 1. 2. 5. 3. 4.
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17. ChipScope Core Instantiation
Choose the chipscope_opb_iba_0 IP instance from the right hand side drop-down box, [CTRL-select] to add the following parameters and set their value from the list:
C_NUM_DATA_SAMPLES = 512 (default)
C_ENABLE_TRIGGER_OUT = 1
C_CONTROL_UNITS = 1
C_ADDR_UNITS = 1
C_DATA_UNITS = 1
C_GENERIC_TRIGGER_UNITS = 1
C_TRIGGER_UNIT_MATCH_TYPE = basic with edges
C_GENERIC_TRIGGER_IN_WIDTH = 1
Click 確定.
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18. ChipScope Core Instantiation
Some control signals to the MicroBlaze processor are required to enable control and triggering between the ChipScope Analyzer and the GDB Debugger. In the system.mhs file add the following two ports under the Microblaze core parameter listing:
PORT MB_Halted = mb_halted
PORT DBG_STOP = dbg_stop
Save and Close the file. 1. 2.
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19. ChipScope Core Instantiation
Select Download to generate the new HW system and link in the SW. Operation should still be the same.
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20. GDB and ChipScope Operation
In XPS select Tools  XMD or using the XMD icon , launch the Xilinx Microprocessor Debugger (XMD) tool.
If a message appears, click 確定 to open the XMD Debug Options box.
Verify that Hardware is selected as the Connection Type and click Save to accept the default settings. 1. 2. 3.
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21. GDB and ChipScope Operation
After saving, you may have to reopen XMD. If so, select Tools  XMD or using the XMD icon , launch the Xilinx Microprocessor Debugger (XMD) tool.
In the XMD dos-type window that opens type mbconnect mdm at the prompt in order to connect between the processor and host computer using the JTAG port.
Note: In the last line presented in XMD
Starting GDB server for “mdm” target (id = 0) at TCP port no 1234, note the port value it may be necessary shortly.
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22. GDB and ChipScope Operation
Return to XPS and select Tools  Software Debugger or using the GNU debugger icon launch the GNU debugger tool. Select the MyProj application in the popup window as shown in following figure. Click OK.
Select Run  Connect to target or simply click on the running man 1. 2. 3.
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23. GDB and ChipScope Operation
A Target Selection dialogue box will appear.
Select
Target : Remote/TCP : XMD
Hostname : localhost
Port : 1234 (or the port value noted above)
And click OK.
The software code will be downloaded to the evaluation board. Code operation will be halted at the first line following the main( ) routine. Proper connection between GDB and the evaluation board can be verified by noting that the colored highlight is green not purple. If you see purple close the XMD and all GDB windows and return to “Starting the Gnu debugger.” 1. 2.
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24. GDB and ChipScope Operation
Select Control  Continue or simply click on the continue icon
Note the 7segments flashing indicating proper system operation.
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25. GDB and ChipScope Operation
Launch the ChipScope Pro Analyzer tool from the 開始  程式集  ChipScope Pro 6.3i  ChipScope Pro Analyzer.
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26. GDB and ChipScope Operation
Click on the Open Cable/Search JTAG chain icon This will identify the devices on the JTAG chain. Select OK.
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27. GDB and ChipScope Operation
The ChipScope Pro Analyzer will open along with default Trigger Setup and Waveform signal windows.
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28. GDB and ChipScope Operation
Select File  Import. In the Signal Import dialogue click on the Select New File button. 2. 1.
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29. GDB and ChipScope Operation
Browse to the XPS design directory and the select the following file X:\EDKLab\Lab6\implementation\chipscope_opb_iba_0_wrapper\ chipscope_opb_iba_0.cdc and click 開啟 as shown in following figure.
The signals associated with the OPB core should be listed in the Trigger Setup and Waveform signal windows. 1. 2.
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30. HW/SW Debug Interaction
Set M0:TRG0:OPB_CTRL OPB_xferAck bit == 1.
Change the Radix of M1:M3 from binary (Bin) to Hexadecimal (Hex) by clicking on the respective boxes and selecting Hex.
Set M1:TRIG1:OPB_ABUS == 8000_1A00 by selecting and adjusting the value box.
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31. HW/SW Debug Interaction
Adjust the Trigger Condition Equation by selecting the box in the TriggerCondition0 dialogue box that appears. Select M0 and Select M1. The Trigger Condition Equation should now display M0 && M1. Click OK. 1. 2. 3.
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32. HW/SW Debug Interaction
Set the trigger window depth to 512 and position to 256.
Consolidate OPB_Abus signals by [Shift-Select]-ing OPB_Abus[31] : OPB_Abus[0]. Right click Add to Bus  New Bus.
Change new bus name from BUS_0 to OPB_Abus[31:0] by right clicking on BUS_0  Rename. 1. 2. 3. 4. 7. 5.
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33. HW/SW Debug Interaction
Repeat process for OPB_Dbus[31..0].
Set up the Output Enable of the Trigger to Pulse (High). This will cross trigger the GDB debugger.
Setup the trigger by selecting Trigger Setup -> Run as shown below. 1. 2. 3.
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34. HW/SW Debug Interaction
The hardware should trigger and then this will cross trigger the SW asynchronous stop in GDB. Basic ChipScope Pro Trigger settings along with simple waveforms are established.
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35. Conclusion
Chipscope HW debug modules can be added as IP modules in EDK, and the ChipScope analyzer can be used in conjunction with GDB, the GNU debugger in EDK, to provide a debug environment that allows cross triggering and debug between hardware and software using a shared JTAG connection.
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