1. Created by Art Kay Presented by Peggy Liska
DC Specifications: input capacitance, leakage current, input impedance, reference voltage range, INL, and DNL TIPL TI Precision Labs – ADCs
Hello, and welcome to the TI Precision Lab introducing DC specifications.
Overall, this section will cover the specifications listed in a typical ADC data sheet.
In this video, we will define input capacitance, leakage current, input impedance, reference voltage range, integral nonlinearity, and differential nonlinearity.
Created by Art Kay
Presented by Peggy Liska

2. Analog Input: Input Capacitance
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ANALOG INPUT
CIN Input capacitance
In sample mode 60 pF
In hold mode 4
Let’s start with input capacitance. The input sample and hold capacitance of a SAR ADC is normally specified in the data sheet. At the top of this slide, we show an excerpt from the ADS9110 datasheet indicating that the input capacitance is typically 60pF when in sample mode and 4pF in hold mode. The SAR ADC simplified model shown on the left helps us get a basic idea of what “sample mode” and “hold mode” mean. In sample mode the switch S1 is closed. This connects the 60pF capacitor to the external signal applied at the input “AIN_P”. The goal of the sampling process is to store the input signal on the sampling capacitor. The sample cycle is often called the “acquisition cycle.” In hold mode, the switch S1 is opened and the ADC will convert the sampled signal. This time period is often called the “conversion cycle”. While in hold mode, the input capacitance is equal to the parasitic capacitance of the input diode structure which is typically 4pF. A more detailed input structure showing the input diodes, resistances, capacitances, and switches is shown on the right.

3. Analog Input: Input Leakage Current
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ANALOG INPUT
IIL Input leakage current ±1 µA
Next, let’s look at input leakage. The input leakage is a dc current that flows into or out of the data converter input pins. This current results from internal ESD protection structures and other parasitic structures. This current can be modeled as a dc current source on both ADC inputs, and is typically in the nano-amp to micro-amp level. You can think of input leakage current to be similar to bias current on the input of an amplifier. Notice that the polarity can be in either direction. The example shown here illustrates how the bias current can generate an offset error when it flows through any source impedance. Notice in this example that a 10uV error signal is developed on each input. In this case the leakage current out of each input is +1uA, but in general the polarity and magnitude may be different depending on device-to-device variation. In fact, the leakage current is given as a typical value so the worst case leakage currents will be larger. The typical value represents plus or minus one standard deviation or 68.3% of the devices manufactured. For an estimate of the maximum you can use plus or minus three standard deviations for 99.7% of the population.

4. Analog Input: Input Impedance
The next specification is input impedance. In many cases, the input impedance of a data converter will be a dynamic impedance. Frequently, the dynamic impedance is the result of input leakage currents as well as the switching and charging of the input capacitance. However, some data converters have an amplifier input with a fixed impedance. The amplifier’s fixed input impedance is generally from the resistance of its gain-setting resistors. The input impedance can be used to calculate an input current, and this input current will generate an error when it flows through any source impedance. In the example shown, the input current is calculated for a 10V input signal for the ADS8681 converter. This current generates an error of 7.5mV when flowing through the 1kΩ source impedance. The 1kΩ source impedance will also generate a gain error in this example as it is in series with the Programmable Gain Amplifier (or PGA) gain-setting resistor. To minimize error it is advisable to minimize source impedance for this type of converter.

5. Reference Input: Reference Input Voltage Range
All specifications are for AVDD = 1.8V, DVDD = 1.8V, VREF = 5V, and fDATA = 2Msps, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ANALOG INPUT
VREF Reference Input Voltage Range
2.5
5.0 V
Next we will look at the reference input voltage range. Most specifications in data converter data sheets will be defined for a specific reference voltage. Typically, this is the most popular reference voltage that will be used with this converter. Using any other reference voltage within the reference input voltage range should yield comparable performance to the specified data sheet performance. In some cases, curves in the data sheet will illustrate how key parameters are affected by different reference voltages. Shown here are some data sheet excerpts from the ADS9110 data sheet. In the data table, the specified reference range of 2.5V to 5.0V is given. The header at the top of the table indicates that the specifications are all defined with a VREF equal to 5V. The curves in the body of the data sheet can be used to better understand how adjusting the reference voltage will affect key parameters.

6. Reference Input: Reference current
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
EXTERNAL REFERENCE INPUT
Reference input current
During conversion, 1MHz sample rate, midcode
300 µA
Input leakage Current
250 pA
CREF
Decoupling capacitor at the reference input 10 22 µF
The next specification to consider is the reference current. The reference input on a SAR data converter is connected to a bank of switched capacitors. During the conversion cycle, these capacitors will be switched into the comparison circuitry and they will charge or discharge to the reference input voltage very rapidly. Typically, for each bit in a conversion cycle you will see a large spike in the reference input current as the internal capacitor charges. The table shows an excerpt from the ADS8881 data sheet indicating that the typical reference input current is 300uA during conversion. Note that the specified current is actually an average current as the actual current will show up as rapid, large spikes (shown as 10 mA in this waveform example). Notice that the entire conversion period may be on the order of 100ns and the time between current spikes may be tens of nano-seconds. Normally, a large filtering capacitor is placed at the reference input to respond to the rapid transient current requirements and the reference will provide the average current needed to replenish the capacitor between the sharp transients. Sometimes a wide bandwidth buffer is required at the reference input to the ADC because of the relatively short time between the transients. Note that the specification table also gives a recommended decoupling capacitor for the reference input.

7. System Performance: Ideal Transfer Function
𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝑪𝒐𝒅𝒆𝒔= 𝟐 𝑵
𝑽 𝑳𝑺𝑩 = 𝑭𝑺𝑹 𝟐 𝑵
Where
VLSB = The minimum resolvable voltage width
FSR = Full Scale Range
N = Number of bits
𝐕 𝐋𝐒𝐁 = 𝐅𝐒𝐑 𝟐 𝐍 = 𝟐𝐕 𝟐 𝟒 =𝟎.𝟏𝟐𝟓𝐕
𝐍𝐮𝐦𝐛𝐞𝐫 𝐨𝐟 𝐂𝐨𝐝𝐞𝐬= 𝟐 𝐍 = 𝟐 𝟒 =𝟏𝟔
In order to discuss nonlinearities of ADCs, we first need to understand the ideal output of an ADC. Here we show the ideal transfer function for an ADC. The horizontal axis represents a continuous analog input signal. The vertical axis shows the digital output codes which can be thought of as levels for rounding off the analog input signal to its nearest digital equivalent. The full scale input range of the ADC is equally divided over the total number of digital output codes to transform the dashed red line in this graph to the staircase blue line shown here.
The number of bits (shown here as N) is the number of binary digits in the digital output code used to represent the full scale analog signal. In this example we have four bits or binary digits. The number of digital output codes is the total number of different binary words available for the digital output. The number of codes here is 16, which corresponds to counting from binary 0000 to 1111 which is 0 to 15 in decimal. Note that you can calculate the number of codes by taking 2 to the power of the number of bits.
The resolution of the converter corresponds to the width of each analog step and is equivalent to the minimum resolvable change in analog input. The resolution is often identified as the width of the least significant bit. This can be computed by taking the full scale range and dividing by the total number of bits, or 2 to the N power. In this example the least significant bit width, or resolution, can be calculated by dividing 2V by 16 to get a resolution of 0.125V. The full scale range in this example is 2V, but the maximum detectable input voltage is the full scale range minus one LSB or 1.875V in this example.

8. System Performance: Differential Nonlinearity (DNL)
𝑫𝑵𝑳 𝒌 = 𝑾 𝒌 −𝑸 𝑸
𝑊 𝑘 =𝑇 𝑘+1 −𝑇[𝑘]
W[k]
the measured code width.
T[k]
The voltage level where a code transitions Q
Ideal code width
The first ADC nonlinearity is differential nonlinearity or DNL. DNL is a measurement of how the width of a code compares to the ideal width. The figure illustrates how some codes are longer than the ideal width and others are shorter. The equation shown illustrates how DNL is calculated. The equation is really an error calculation using the measured code width, W[k], and the ideal code width Q. The measured code width is calculated by subtracting the two adjacent code transitions, T[k] and T[k-1]. If the measured code width is equal to the ideal code width, the DNL is zero. If the measured code is longer than the ideal code, the DNL is positive. And if the measured code is shorter, the DNL is negative.

9. System Performance: No Missing Code (NMC)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
NMC
Integral Nonlinearity
AVDD = 3V  12
Bits
In some cases the dynamic non-linearity is large enough to cause a code transition to be completely skipped. This is called a missing code. The example here shows a case where the digital output of the ADC completely skips the code In this example, there is no analog input signal that will ever cause the digital output to read Missing codes can be a serious issue for many electronic systems, so most modern ADCs are designed and tested to ensure that they will not have this problem. In fact, data sheets often provide a no missing code, or NMC, specification to highlight that the converter will not have missing codes. The excerpt above shows an example of the no missing codes specification.

10. Differential Nonlinearity (DNL) vs. Code
PARAMETER ADS9110
TEST CONDITION
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
DNL
Differential Nonlinearity
AVDD = 1.8V 
-0.75
±0.4 
+0.75
LSB
This slide shows an example of how the differential nonlinearity specification is shown in data sheets. For each code in the transfer function, we compare the measured code width to the ideal code width. Thus, one way that this specification can be displayed is a graph of DNL versus ADC output code. In our simplified example, you can see the DNL versus ADC code for a 3-bit converter. The calculation for code 101 is shown. This bit is 0.031V wide which is short compared to the ideal width of 0.125V so the DNL is negative. The plot on the right shows a more practical example of an 18-bit converter. In this case thousands of DNL measurements are being displayed and you can see that the DNL is typically less than 0.5 LSB. At the top of the page is an example of a DNL specification. The minimum and maximum limits on this specification indicate that all ADC codes are tested and the DNL will be less than ±0.75 LSB for all passing devices.

11. System Performance: Integral Nonlinearity (INL)
The second nonlinearity is integral nonlinearity or INL. INL is a measurement of how close the measured ADC transfer function compares to a straight line. To eliminate errors from gain and offset error, the measured transfer function is compared to an ideal straight line that is fit to the end points of the ADC transfer function. The deviation between the ideal line and the measured function is the INL error. In the simplified example shown, the green dashed line is the end point fit of the transfer function. The reason it is called an end point fit is that the green line starts at the first code, 0000, and ends on the last code, For a perfectly linear ADC, the straight line fit would be directly down the middle of the ADC transfer function. In this case, however, you can see that the measured function, shown in blue, deviates away from the linear fit, so it is said to have a positive INL error. As with DNL error, the integral nonlinearity can be displayed versus the ADC output code. Integral nonlinearity may be given units of LSB codes or it may be given as a percentage of the full scale range.

12. INL Data Sheet Specification
PARAMETER ADS9110
TEST CONDITION
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
INL
Integral Nonlinearity
AVDD = 3V 
-1.5
±0.5 
1.5
LSB
An example of the data sheet specification for INL as well as a graph of typical integral nonlinearity for an ADC versus output code are shown here. In the case of the data sheet table, the INL is tested for all codes and will be less than 1.5 LSBs. Devices with an INL error that exceeds 1.5 LSBs are discarded. The typical INL is an indication of the performance for most devices. The typical range is mathematically set during characterization to be plus or minus one standard deviation of the population. This means that about 68.3% of the population is within the typical range. Notice that the graph illustrates the typical integral nonlinearity in LSBs versus output code for this device.

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