1. Chapter 5a On-Chip Power Integrity
Prof. Lei He
Electrical Engineering Department
University of California, Los Angeles
URL: eda.ee.ucla.edu

2. Outline
Introduction to power integrity
On-chip current modeling
On-chip de-cap insertion

3. 3 Introduction Power noise (ground bounce, Vdd droop, Vdd drop)
The integral of noise is what matters 3 3

4. Pad ... 4 Introduction IR drops:
Voltage difference between power supply pads and individual cell instances.
Electro-migration:
Metal ion mass transport along the grain boundaries when a metallic interconnect is stressed at high current density. Mean Time to Failure (MTF) (Black’s equation):
...
Pad 4 4

5. 5 Power Noise Power noise (ground bounce, Vdd droop)  IR + L*di/dt
IR drop is the primary on-chip power noise, especially when flip chip is used
L*di/dt noise most time is not an on-chip concern, except for high-performance design
SSN (simultaneous switching noise) is primarily L*di/dt noise for IO cells, package and PCB
SSO: simultaneous switching output noise 5 5

6. Simultaneous Switching Noise
SSN is most signicantly observed around the output pads of the chip.
in order to drive large off-chip loads, the I/O buffers are usually very large in size, drawing a significant amount of instantaneous currents when they switch.
in clock synchronized chips multiple I/O buffers tend to switch simultaneously to create a large surge current with a sharp slope.
the parasitic inductance of the power distribution network of the package, including the interconnections to both the chip and the board, is usually in the range of a few hundred pico-Henries. 6 6

7. Circuit to Generate SSN7 7

8. Outline
Introduction to power integrity
On-chip current modeling
On-chip de-cap insertion

9. On-Chip Current Models
Static current model for IR drop
Worst case based on test vectors
Average case (either based on test vectors, or assume certain percent of gates are switching)
So-called vector-less model
Partition circuit into blocks
Find worst-case current for each block via exhaustive testing
Sum up worst-case current
Transient current model for L di/dt noise
Find peak current, and assume a switching time
Stochastic model considering logic-induced and temporal correlation 3 9

10. Design for on-chip Power Integrity
Static current model for IR drop
Power/ground sizing
Transient current model for L di/dt noise
On-chip de-cap allocation
De-cap can be implemented by CMOS FET, or trench-cap
De-cap value is continuous 3 10

11. Power Noise of a chip with peripheral IO
A real industrial chip
#cell instances: 0.5M
#P/G resistors: 0.6M

12. P/G Sizing
Unrestricted IR drops and current densities in power / ground (P/G) network will cause malfunction and reliability problems in deep sub-micron IC chips.
Increased cell delays (timing problem)
increased resistance and even opens of P/G wires
P/G sizing in two steps
P/G network construction (P/G routing) to decide P/G pitches and tapping-points connecting to package power supply
Determination of wire segment widths 3 12

13. Effect of de-cap
Adding decaps is the most effective way to reduce L di/dt noise in P/G grids 13

14. Costs of decap Decaps are mainly made of MOS gate capacitors
Consuming premium white spaces
White space can otherwise be used for adding buffers, other logic gates for physical optimization.
MOS gates are leaky or become more leaky with scaling
More leakage powers
Excessive decap may lead to low yield and low circuit resonant frequency
Economic use of decap is important!! 14

15. Decap Budgeting Overview
Nodes away from Vdd pin may suffer from supply noise due to sudden burst of activity
Provide current for surplus need from the local storage charge
Location matters
The closer to the turbulent point, the more noise reduction can be achieved
Given the amount of decap to be inserted, find the optimal location so that the noise can be suppressed to a maximum extent.
Load current
power supply
intrinsic
cap
decap
We define the noise as the integral over time of the area below Vn t0 t1 15

16. Decap Budgeting Problem Formulation
Objective
Find the distribution and location of the white space so the noise on power network is minimized
Constraints:
Local decap constraints: amount of decap allowed at each location is limited due to placement constraint
Global decap constraints: total amount of decap allowed is limited due to leakage constraint
Limitation of most existing work:
Most existing work in essence uses worst case load current in order to guarantee there is no noise violation, which is too pessimistic
It is not clear how to provide decap budgeting solution that is robust to current loads under all kinds of operations for a circuit

17. Correlated Load Currents
Strong correlation between load currents due to
Operation variation
Currents at different ports have logic-induced correlation
Large number of ports with limited control bits
Currents at certain ports cannot reach maximum at the same time due to the inherent logic dependency for a given design
Currents at the same port have temporal correlation
System takes several clock cycles to execute one instruction
The currents cannot reach maximum at all the clock cycles
Process variation
Currents have intra-die variation due to process variation
The P/G network is robust to process variation, but the load currents have intra-die variation because the circuit suffers from process variation.
Leff variation is one of the primary variation sources and the variation is spatially correlated

18. Current Sampling
Model the current in each clock cycle as a triangular waveform and assume constant rising/falling time
Other current waveforms can be used. It will not affect the algorithm
In our verification, we use the detailed non-simplified current waveform
Partition a circuit into blocks and assume no correlation between different blocks
Extensive simulation for each block to get the peak current value in each clock cycle and at each port.
Assume there is only temporal correlation within certain number of clock cycles L
L can be the number of clock cycles to execute certain function

19. Stochastic Current Modeling
Divide peak current values into different sets according to the clock cycle and port number
The set contains peak current values at port k and in clock cycle j, j+L, j+2L,…
Example: Take L=2, and consider two ports in 8 consecutive clock cycles
Define to be the stochastic variable with the sample set
For example, has the samples 0.1, 0.3, 0.5, 0.7, and therefore has mean value 0,4
The correlation between and reflects the temporal correlation between clock cycle j1 and j2
The correlation between and reflects the logic induced correlation between port k1 and k2.
clock cycles j, temporal correlation
port k,
logic-induced correlation 20

20. Extraction of Correlations
The logic-induced correlation coefficient between port k1 and k2 at clock cycle j can be computed as
Temporal correlation coefficient between clock cycle j1 and j2 at port k can be computed as
To take process variation into consideration, sample each multiple times over different region, and the above two formulas can still be applied
We use the general definition of correlation coefficient. In our case, we have two. 21

21. Extraction of Correlations
As is not Gaussian, apply Independent Component Analysis to remove the correlation between and get a new set of independent variables r1, r2, …
Each can be represented by the linear combination of r1, r2,…
Accordingly the waveform at each clock cycle can be reconstructed from those r1,r2,…, i.e.,
The new variables ri catch both the operation and process variations.
We use the general definition of correlation coefficient. In our case, we have two. 22

22. Example of Extracted Temporal Correlation
The correlation map for peak currents between different clock cycles of one port from an industry application.
The P/G network is modeled as RC mesh
The load currents are obtained by detailed simulation of the circuit
It can be seen that the correlation matrix can be clearly divided into four trunks, and L can be set as 10 23

23. Parameterized MNA Formulation
Original MNA formulation
With the design variables - decap area wi, the G, C matrices can be expressed as
Together with the stochastic current model, the MNA formulation becomes:
With parameters wi and ri
The objective now is to find the optimal solution for those parameters
More specifically, find the wi values that minimize the noise with the ri corresponding to the load currents which introduce the maximum noise 24

24. Stochastic Decap Formulation
Minimize the maximum noise sum over all ports
Subject to the stochastic current variable upper/lower bound
Subject to
Local decap area constraint due to placement constraint
Global decap area constraint due to leakage constraint
Non-convex min/max optimization problem
Difficult to find global optimal solution 25

25. Iterative Programming Algorithm
Each iteration we increase the white space allowed until all the white space has been used up or it converges
Find the optimal decap budgeting for the giving max droop/bounce
update the max droop/bounce
update the decap budgeting
Find the input corresponding to the max. droop/bounce for the given decap budgeting
Cannot guarantee optimality, but can guarantee convergence and efficiency
Experimental results show our algorithm can achieve good optimization results 26

26. Illustration of Iterative Programming
A3: (P3)
A1: (P3)
A0: Initial
A2: (P2)
A0: Initial noise curve at one randomly selected port
A1: The noise curve under the optimal decap budgeting for a giving droop/bounce
A2: The noise curve with the input corresponding to the max. droop/bounce for the decap budgeting in A1
A3: The noise curve under the optimal decap budgeting for the giving max droop/bounce in A2 27

27. Sequential Programming
We apply sequential linear programming (sLP) to solve each of the two sub-problems. For each sub-problem, we iteratively do the following two steps until the solution converges:
Compute the sensitivities of all the variables to the first order by moment matching.
Linearize the objective function with the sensitivities and the optimization problem becomes an LP
first order sensitivities 28

28. Impact of Current Correlations
Model 1
Maximum current at all ports
Model 2
Stochastic model with logic-induced correlation
Model 3
Model 2 + temporal correlation
Node #
Noise (V*s)
Runtime (s)
Model 1
Model 2
Model 3
1284
6.33e-7
1.28e-7
4.10e-8
104.2
161.2
282.3
10490
5.21e-5
1.09e-5
4.80e-6
973.2
1430
2199
42280
7.92e-4
5.38e-4
9.13e-5
2732
3823
5238
166380
1.34e-2
5.37e-3
2.28e-3
3625
5798
7821
avg 1
1/2.68X
1/9.10X
1.50X
2.26X
Compared with the model assuming maximum currents at all ports, under the same decap area,
Stochastic model with spatial correlation only reduce the noise by up to 3X
Stochastic model with both spatial and temporal correlation reduce the noise by up to 9X 29

29. Impact of Leff Variation
Node # X
V.R.
sLP
sLP + Leff
mean (V*s)
std (V*s)
runtime (s)
1284
10%
9.28e-7
3.97e-7
184.2
6.14e-7
1.38e-7 X
20%
9.43e-7
4.55e-7
6.38e-7
1.86e-7
10490
1.03e-4
4.79e-5
1121
7.22e-5
1.23e-5 X
1.22e-4
4.38e-5
7.94e-5
2.06e-5
42280
2.29e-3
9.72e-4
2236
8.23e-4
1.01e-4 X
4.43e-3
1.01e-3
8.28e-4
1.92e-4
166380
2.06e-2
9.91e-3
3824
5.31e-3
8.92e-4 X
2.31e-2
1.03e-2
5.92e-3
9.33e-4
avg 1
1/2.02X
1/5.05X
2.73X
1/1.95X
1/4.05X
Compared with the stochastic model without considering Leff variation, the stochastic model with it reduce the average noise by up to 4X and the 3-sigma noise by up to 13X 30

30. Re-cap of Key Points
IR drop is primarily an on-chip issue and can be fixed by P/G sizing
Beyond chip, L di/dt (or SSN) is the primarily concern
On-chip decap is continuous and is allocated to the white-space on the chip
On-chip current (not IO current yet) can be modeled by worst case, average case, and stochastic models 31

31. Dynamic noise: L di/dt noise
Reading Assignment
Static noise: IR drop
S. Tan and R. Shi, “Optimization of VLSI Power/Ground (P/G) Networks Via Sequence of Linear Programmings”, DAC’09
Dynamic noise: L di/dt noise
Yiyu Shi, Jinjun Xiong, Chunchen Liu and Lei He, "Efficient Decoupling Capacitance Budgeting Considering Current Correlation Including Process Variation", ICCAD, San Jose, CA, Nov
Supplementary reading:
H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Power Grid Analysis Using Random Walks,” IEEE Trans. on CAD, 2005.
Yiyu Shi, Wei Yao, Jinjun Xiong, and Lei He, "Incremental and On-demand Random Walk for Iterative Power Distribution Network Analysis", ASPDAC 2009