1. CMOS VLSI Design Chapter 12 Memory
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slides from David Harris
adapted by Duncan Elliott
Textbook: CMOS VLSI Design - A Circuits and Design Perspective, 4th Edition, N. H. E. Weste & D. Harris
CH 12 Memory

2. Outline Memory Arrays SRAM Architecture SRAM Cell Decoders
Column Circuitry
Multiple Ports
CAMS
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3. Memory Arrays
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4. Array Architecture 2n words of 2m bits each
If n >> m, fold by 2k into fewer rows of more columns
Good regularity – easy to design
Very high density if good cells are used
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5. 12T SRAM Cell Basic building block: SRAM Cell
Holds one bit of information, like a latch
Must be read and written
12-transistor (12T) SRAM cell
Use a simple latch connected to bitline
46 x 75 l unit cell
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6. SRAM large area (6T with N-well) logic CMOS process compatible
higher static power
volatile
fast
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7. 6T SRAM Cell Cell size accounts for most of array size
Reduce cell size at expense of complexity
6T SRAM Cell
Used in most commercial chips
Data stored in cross-coupled inverters
Read:
Precharge bit, bit_b
Raise wordline
Write:
Drive data onto bit, bit_b
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8. SRAM Read Precharge both bitlines high Then turn on wordline
One of the two bitlines will be pulled down by the cell
Ex: A = 0, A_b = 1
bit discharges, bit_b stays high
But A bumps up slightly
Read stability
A must not flip
N1 >> N2
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9. SRAM Write Drive one bitline high, the other low Then turn on wordline
Bitlines overpower cell with new value
Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
Force A_b low, then A rises high
Writability
Must overpower feedback inverter
N2 >> P1
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10. SRAM Sizing High bitlines must not overpower inverters during reads
But low bitlines must write new value into cell
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11. SRAM Column Example
Read Write
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12. SRAM Layout
Cell size is critical: 26 x 45 l (even smaller in industry)
Tile cells sharing VDD, GND, bitline contacts
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13. CH 12 Memory

14. Thin Cell SRAM In nanometer CMOS
Avoid bends in polysilicon and diffusion
Orient all transistors in one direction
Lithographically friendly or thin cell layout fixes this
Also reduces length and capacitance of bitlines
[R W Mann]
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15. Commercial SRAMs Five generations of Intel SRAM cell micrographs
Transition to thin cell at 65 nm
Steady scaling of cell area
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16. Decoders n:2n decoder consists of 2n n-input AND gates
One needed for each row of memory
Build AND from NAND or NOR gates
Static CMOS Pseudo-nMOS
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17. Decoder Layout Decoders must be pitch-matched to SRAM cell
Requires very skinny gates
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18. Large Decoders For n > 4, NAND gates become slow
Break large gates into multiple smaller gates
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19. Predecoding Many of these gates are redundant Factor out common
gates into predecoder
Saves area
Same path effort
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20. CH 12 Memory

21. CH 12 Memory

22. Column Circuitry Some circuitry is required for each column
Bitline conditioning
Sense amplifiers
Column decoding
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23. Bitline Conditioning Precharge bitlines high before reads
Equalize bitlines to minimize voltage difference when using sense amplifiers
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24. Sense Amplifiers Bitlines have many cells attached
Ex: 32-kbit SRAM has 128 rows x 256 cols
128 cells on each bitline
tpd  (C/I) DV
Even with shared diffusion contacts, 64C of diffusion capacitance (big C)
Discharged slowly through small transistors (small I)
Sense amplifiers are triggered on small voltage swing (reduce DV)
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25. Differential Pair Amp Differential pair requires no clock
But always dissipates static power
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26. Clocked Sense Amp Clocked sense amp saves power
Requires sense_clk after enough bitline swing
Isolation transistors cut off large bitline capacitance
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27. Twisted Bitlines Sense amplifiers also amplify noise
Coupling noise is severe in modern processes
Try to couple equally onto bit and bit_b
Done by twisting bitlines
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28. Column Multiplexing
Recall that array may be folded for good aspect ratio
Ex: 2 kword x 16 folded into 256 rows x 128 columns
Must select 16 output bits from the 128 columns
Requires 16 8:1 column multiplexers
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29. Tree Decoder Mux Column mux can use pass transistors
Use nMOS only, precharge outputs
One design is to use k series transistors for 2k:1 mux
No external decoder logic needed
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30. Single Pass-Gate Mux
Or eliminate series transistors with separate decoder
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31. Ex: 2-way Muxed SRAM
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32. Multiple Ports We have considered single-ported SRAM
One read or one write on each cycle
Multiported SRAM are needed for register files
Examples:
Multicycle MIPS must read two sources or write a result on some cycles
Pipelined MIPS must read two sources and write a third result each cycle
Superscalar MIPS must read and write many sources and results each cycle
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33. Dual-Ported SRAM Simple dual-ported SRAM
Two independent single-ended reads
Or one differential write
Do two reads and one write by time multiplexing
Read during ph1, write during ph2
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34. Multi-Ported SRAM Adding more access transistors hurts read stability
Multiported SRAM isolates reads from state node
Single-ended bitlines save area
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35. Large SRAMs Large SRAMs are split into subarrays for speed
Ex: UltraSparc 512KB cache
4 128 KB subarrays
Each have 16 8KB banks
256 rows x 256 cols / bank
60% subarray area efficiency
Also space for tags & control
[Shin05]
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36. Serial Access Memories
Serial access memories do not use an address
Shift Registers
Tapped Delay Lines
Serial In Parallel Out (SIPO)
Parallel In Serial Out (PISO)
Queues (FIFO, LIFO)
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37. Shift Register Shift registers store and delay data
Simple design: cascade of registers
Watch your hold times!
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38. Denser Shift Registers
Flip-flops aren’t very area-efficient
For large shift registers, keep data in SRAM instead
Move read/write pointers to RAM rather than data
Initialize read address to first entry, write to last
Increment address on each cycle
Also good for crossing clock boundaries
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39. CAMs Extension of ordinary memory (e.g. SRAM)
Read and write memory as usual
Also match to see which words contain a key
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40. 10T CAM Cell Add four match transistors to 6T SRAM 56 x 43 l unit cell
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41. CAM Cell Operation Read and write like ordinary SRAM For matching:
Leave wordline low
Precharge matchlines
Place key on bitlines
Matchlines evaluate
Miss line
Pseudo-nMOS or dynamic NOR of match lines
Goes high if no words match
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43. DRAM compact area with DRAM process low static power volatile
slow to mid speed
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44. CH 12 Memory

45. Stacked One-T DRAM [Asanovic] 1-T DRAM Cell word access transistor bit
Storage
capacitor (FET gate, trench, stack)
VREF
TiN top electrode (VREF)
Ta2O5 dielectric
W bottom
electrode
poly
word
line
access transistor
[Asanovic]
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54. Read-Only Memories Read-Only Memories are nonvolatile
Retain their contents when power is removed
Mask-programmed ROMs use one transistor per bit
Presence or absence determines 1 or 0
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55. ROM Example 4-word x 6-bit ROM Represented with dot diagram
Dots indicate 1’s in ROM
Word 0:
Word 1:
Word 2:
Word 3:
Looks like 6 4-input pseudo-nMOS NORs
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56. ROM Array Layout Unit cell is 12 x 8 l (about 1/10 size of SRAM)
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57. Row Decoders ROM row decoders must pitch-match with ROM
Only a single track per word!
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58. Complete ROM Layout
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59. CH 12 Memory

60. Process cross section?
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61. PROMs and EPROMs Programmable ROMs
Build array with transistors at every site
Burn out fuses to disable unwanted transistors
Electrically Programmable ROMs
Use floating gate to turn off unwanted transistors
EPROM, EEPROM, Flash
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62. Flash Programming Charge on floating gate determines Vt
Logic 1: negative Vt
Logic 0: positive Vt
Cells erased to 1 by applying a high body voltage so that electrons tunnel off floating gate into substrate
Programmed to 0 by applying high gate voltage
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63. NAND Flash High density, low cost / bit Programmed one page at a time
Erased one block at a time
Example:
4096-bit pages
16 pages / 8 KB block
Many blocks / memory
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64. 64 Gb NAND Flash 64K cells / page 4 bits / cell (multiple Vt)
64 cells / string
256 pages / block
2K blocks / plane
2 planes
[Trinh09]
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