1. CALICE Readout Front End FPGA Development
O. Zorba
CALICE 23/10/2003
© Imperial College London

2. Progress Report Investigated the implication of using slower FPGA
Re-development of Trigger Delay circuit with XC2V1000-FG456-4 (slower FPGA)
Logic Design of VFE Control Signals with slower FPGA
O. Zorba
CALICE 23/10/2003
© Imperial College London

3. Block Diagram CLK Distribution DAC Control Configuration
HOLD
RESET
SRIN
MUXCLK
ENABLE (6)
ID (6)
VFE Logic
Calibration and Trigger delay Logic
TCALIB1-2
ADC Control
ADC SERIAL DATA
ADC CLK and Control
Control Logic
Configuration
EVENT DATA
Trigger
EVENT DATA OUTPUT CONTROL
CLK
CLK Distribution
Configuration I/O Control
© Imperial College London

4. VFE Control Logic
O. Zorba
CALICE 23/10/2003
© Imperial College London

5. Future Work Testing of VFE Control Logic
Development of Control and Configuration Logic
Emulate the design on the FED board
O. Zorba
CALICE 23/10/2003
© Imperial College London