1. LUT Structure for Delay: Cluster or Cascade?
Alan Mishchenko
University of California, Berkeley

2. Outline LUT structures proposed recently
S. Ray, A. Mishchenko, N. Een, R. Brayton, S. Jang, and C. Chen, "Mapping into LUT structures", Proc. DATE'12.
There are several types of LUT structures
Cluster Cascade
Which one is better for delay optimization?

3. Delay Assumptions Average wire delay is ~4x of average LUT delay
LUT pin delay is d*(i+1), where i is pin number
In this project, we assume
routable wire delay 0.7
non-routable wire delay 0
LUT pin delays (0.05, 0.10, 0.15, 0.20, 0.25, 0.30)
This leads to the following LUT library:
# The area/delay of k-variable LUTs:
# k area delay

4. Observations 66 cluster is the same as 66 cascade
Cluster has better delays than cascade
Cluster 666 has the best near-critical ratios
Near-critical ratio are a ratio of primary outputs whose delay is within 10% of the most critical one, divided by the total number of primary outputs

5. Cluster Delays

6. Cluster Near-Critical Ratios

7. Cascade Delays

8. Cascade Near-Critical Ratios

9. Delay Comparison

10. Near-Critical Ratio Comparison

11. Conclusion Compared two types of LUT structures
Cluster vs. Cascade
Reviewed structural methods for technology mapping into LUT structures
Experimented with several benchmark suites, initially mapped into 6-LUTs, followed by mapping into LUT structures
Concluded that
Cluster is better than Cascade
Cluster 666 is the best!

12. Abstract
This talk represent a comparison of several types of LUT structures for delay optimization. Realistic assumptions about the delays of routable and non-routable connections are used. The conclusion is that the cluster structure leads to better delays. It is also easier to handle in the technology mapper. Finally, it leads to mapped networks with a smaller ratio of near-critical outputs.
Alan Mishchenko graduated from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 and Glushkov Institute of Cybernetics (Kiev, Ukraine) in From 1998 to 2002 he was an Intel-sponsored researcher at Portland State University. In 2002, he joined the EECS Department at UC Berkeley, where he is currently an associate researcher. Alan is interested in efficient methods for synthesis and verification.