1. Example: Re-design with Moore Model
The state table is shown below
Memory requires more states in the Moore model: “Moore is More.”
A/0
B/0
C/0
D/0
E/1 1
Present
State
Next State
x=0 x=1
Output y A B C D E 1
KU College of Engineering
Elec 204: Digital Systems Design

2. Sequential Design: Example 3
Design a sequential modulo 3 accumulator for 2-bit operands
Definitions:
Modulo n adder - an adder that gives the result of the addition as the remainder of the sum divided by n
Example: modulo 3 = remainder of 4/3 = 1
Accumulator - a circuit that “accumulates” the sum of its input operands over time - it adds each input operand to the stored sum, which is initially 0.
Stored sum: (Y1,Y0), Input: (X1,X0), Output: (Z1,Z0)
KU College of Engineering
Elec 204: Digital Systems Design

3. KU College of Engineering Elec 204: Digital Systems Design
Example 3 (continued)
Complete the state diagram:
A/00 00
Reset 01
C/10
Add arc labeled 10 from state A to state C
Add arc labeled 00 from state B to state B
Add arc labeled 01 from state B to state C
Add arc labeled 10 from state B to state A
Add arc labeled 00 from state C to state C
Add arc labeled 01 from state C to state A
Add arc labeled 10 from state C to state B
B/01
KU College of Engineering
Elec 204: Digital Systems Design

4. KU College of Engineering Elec 204: Digital Systems Design
Example 3 (continued)
Complete the state table
State Assignment: (Y1,Y0) = (Z1,Z0)
Codes are in gray code order to ease use of K-maps in the next step
X1X0
Y1Y0 00 01 11 10
Z1Z0
Y1(t+1), Y0(t+1)
A (00) X
B (01)
- (11)
C (10)
Add entry 01 in (00),(01)
Add entry 10 in (00)(10) Add entry 01 in (01)(00)
Add entry 10 in (01)(01)
Add entry 00 in (01)(10)
Add entry 10 in (10)(00)
Add entry 00 in (10)(01)
Add entry 01 in (10)(10)
KU College of Engineering
Elec 204: Digital Systems Design

5. KU College of Engineering Elec 204: Digital Systems Design
Example 3 (continued)
Find optimized flip-flop input equations for D flip-flops
D1 =
D0 = D1 Y0 Y1 X1 X0 X D0
Entries in locations 0 through 15 for D1 = 0,0,1,X; 0,1,0,X;1,0,0,X; X,X,X,X
Entries in locations 0 through 15 for D0 = 0,1,0,X; 1,0,0,X;0,0,1,X; X,X,X,X
Prime implicants (all essential) are given in the equations below:
D1 = Y1X1’X0’ + Y0X0 + Y1’Y0’X1
D0 = Y0X1’X0’ + Y1X1 + Y1’Y0’X0
KU College of Engineering
Elec 204: Digital Systems Design

6. Circuit - Final Result with AND, OR, NOTX1 D C R Y1 Z1 X0 Y0 D Z0 C R
Reset
Clock
KU College of Engineering
Elec 204: Digital Systems Design

7. KU College of Engineering Elec 204: Digital Systems Design
Example
Design a clock synchronous sequential circuit with two inputs A, B and a single output Z that is 1 if:
A had the same value at each of the two previous clock ticks, or
B has been 1 since the last time that the first condition was true.
Otherwise, output should be 0.
KU College of Engineering
Elec 204: Digital Systems Design