1. FPGA IMPLEMENTATION OF NIST P-384 MODULAR MULTIPLIER
Yangpingqing Hu, Yuqiu Jiang, Weizhong Wang

2. Objective Implementation with FPGA Good performance per watt feature
Maximize the utilization of modern FPGA features

3. Approach Three stage structure Multiplication Addends sorting
Addition and modular reduction

4. Approach

5. Multiplication
DSP task assignment

6. Multiplication
Output concatenation

7. Multiplication
Output concatenation

8. Sorting addends
NIST recommended Elliptic Curves algorithm

9. Sorting addends

10. Addition

11. Modular Reduction

12. Computation time(Latency)
Utilization
Our
Kung [2], virtex-5
Kung [2], virtex-4
Guneysu [3], 256-bit
Ananyi[4], 384-bit
Frequency(MHz) 50
251.3
182.0
490 60
Slices
4689
1980
7020
1715
20793
BRAM 59 2 4 11
DSP 43 7 8 32
LUT
12827
6115
12435
2589
Computation time(Latency)
5.65ms
11.81ms
16.31ms
0.62ms
19.9ms

13. Calculation Speed Ours Guneysu [3] 256-bit Ananyi[4], 384-bit
Cycles per MUL 32 70
178
Cycles per ADD/SUB 46 18 43

14. Future Work
Complete design of ECC
Support more NIST prime numbers

15. Thank you!