1. MIPS Single and Multi Cycle Data Paths Mite 2
Ellen Spertus
MCS 111
October 31, 2002

3. Today MIPS: single-cycle datapath MIPS: multi-cycle datapth
Review
Definitions
Timing
Instructions to control bits
MIPS: multi-cycle datapth
Lab: Mite 2

4. Big picture
We want to be able to use the same hardware to interpret different types of instructions.
Control signals allow this, by
controlling which path of a multiplexer is enabled
controlling whether writes are performed
controlling ALU behavior
The control unit generates control signals from the bits in the instruction word.

5. Definitions (HP, p. 14) Control Datapath The “brain” of the computer
Tells the datapath, memory, and i/o devices what to do according to the instructions
Datapath
The “brawn” of the computer
Performs arithmetic operations

6. Datapath with control unit
Figure 5.22

7. From instruction bits to control bits

8. Single-cycle datapath
What we’ve been studying for the past two weeks.
Each instruction takes one clock cycle
There is one set of control signals for each instruction
Mite uses a single-cycle datapath

9. Datapath with control unit
2 ns
2 ns
2 ns
1 ns
What should the cycle time be?

10. Function units used by the instruction class
Clock cycle time
Instruction class
Function units used by the instruction class
cycle time =
Stage/ time (ns)
Instruction fetch (2)
Register read (1)
ALU (2)
Memory (2)
Register write (1)
Total
r-format lw sw
branch
jump

11. Disadvantages of single-cycle MIPS
All instructions take the same amount of time — the time of the slowest instruction
Pieces of hardware are duplicated
Memory
ALU

12. Multicycle implementation
Instructions take different amounts of time, depending on the number of stages they require
Hardware can be reused
ALU
Memory
Disadvantage: More complex control

13. Multicycle datapath
Note that there is just one ALU and memory unit.

14. add $r1, $r2, $r3 2 3 1

15. Comparison Single-cycle Each instruction takes one clock cycle.
There is one set of control signals for each instruction.
The clock period is the length of the slowest instruction.
Multi-cycle
Each instruction takes multiple clock cycles.
There is one set of control signals for each cycle of each instruction.
The clock period is the length of the slowest stage.

16. Instruction time: multi-cycle
Instruction class
Function units used by the instruction class
cycle time =
Stage/ time (ns)
Instruction fetch (2)
Register read (1)
ALU (2)
Memory (2)
Register write (1)
Total
r-format lw sw
branch
jump

17. Multicycle summary
Allows instructions using fewer stages (such as ) to run more quickly than instructions requiring more stages (such as ).
Requires more complicated control and temporary registers than single-cycle.
Allows hardware (such as ) to be reused with an instruction.

18. Mite 2 Add a program counter and instruction memory to Mite.
Due date: Friday, Nov. 15.

19. LS163: 4-bit synchronous counter
If reset’, set outputs (Q3..Q1) to zero
If load’, set outputs to inputs (P3..P1)
If enable and Cin, increment outputs
What do you think is in the 163?

20. EPROMs Electronically Programmable Read-Only Memory 27C256 Controls
32K addressable bytes
8 bits per byte
Controls
Chip enable (CE’) low
Output enable (OE’) low
Programming voltage (Vpp) high

21. Mite 1

22. Mite 2

23. Hexadecimal

24. Program