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Design of an Arithmetic Logic Unit (ALU)
VLSI M/360R Lab 2 Design of an Arithmetic Logic Unit (ALU)
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Lab 2 Goals Become Familiar with Gate Level Design Flow
Learn More Tools Design and Optimize for Speed Choose a good structure Perform logic reduction Compete in Speed Spend More Time in the Lab
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Arithmetic Logic Unit (alu)
b[15:0] 16 16 a b 5 code[4:0] vout cin alu cout 16 c[15:0]
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Arithmetic Logic Unit (alu)
b[15:0] cin 16 16 Logic Compare Shifter Adder 5 MUX code[4:0] vout 16 cout c[15:0]
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Logic Arithmetic A OR B A XOR B NOT A A AND B a[15:0] b[15:0]
code[4:0] Logic c[15:0]
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Condition Operation Less than Less than or equal Greater than
Greater than or equal Equal Not equal a[15:0] b[15:0] code[4:0] Compare c[15:0]
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Shifter Logic Left Logic Right Arithmetic Left Arithmetic Right
Rotate Left Rotate Right a[15:0] b[15:0] code[4:0] Shifter c[15:0]
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Shifter Logic shifts should shift in 0's
Arithmetic left shift should shift in 0's Arithmetic right shift should shift in the most significant bit Rotate left shift should shift out the most significant bit to the least significant bit Rotate right shift should shift out the least significant bit to the most significant bit
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16-bit Adder 16-bit adder a[15:0] b[15:0] cin code[4:0] vout cout
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16-bit Adder Options Signed addition Unsigned addition
Signed subtraction Unsigned subtraction Signed increment Signed decrement
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16-bit Addition cin 1 a[15:0] 1 1 1 1 1 1 b[15:0] 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 b[15:0] 1 1 1 1 1 1 1 1 1 c[15:0] 1 1 1 1 cout vout Overflow
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Overflow (vout) Indicates Your Result Is Wrong
The result exceeds the data width Situations That Can Cause Overflow P + P = N N + N = P P – N = N N – P = P
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Compete in Speed at this Point
Design Flow in Lab 2 Design Derive schematic Verify Functionality Compete in Speed at this Point Timing Analysis Place & Route Timing Analysis
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Design Text - Chapter 11, Section 2 Class notes
External experience/research Innovation Family secret
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Schematic Design Given standard cells complete with timing information
INVX1, INVX4, NAND2X1, NOR3X1 No other components allowed (unless designed with standard cells) No memory elements Number indicates drive strength
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Verify Functionality Tool: Verilog-XL
Verify the gate level verilog netlist you design Write testfixture.verilog with test cases given on the web
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Timing Analysis Tool: Primetime
Text-based static timing analysis (STA) Reads in gate level verilog netlist Outputs critical path and delay
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Primetime STA
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Place & Route Tool: Encounter
Layout completed by auto place and route (APR) Run timing analysis pre and post-layout (alu only)
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Layout
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Grading Lab A Lab B Part A takes 50% of total score in Lab 2
Functional Correctness: 30% Performance: 15% (Your max delay) Lab Report: 5% (Your explanation of your design) Lab B Part B takes 50% of total score in Lab 2 Functionality Correctness: 25% Speed: 15% APR correctness: 5% Lab Report: 5%
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