1. Day 26: November 1, 2013 Synchronous Circuits
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 26: November 1, 2013
Synchronous Circuits
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2. Today Clocking Timing discipline Latches Registers
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3. Accumulator Consider an accumulator based on your 16b adder:
What can change the observed delay of this accumulator?
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4. Challenge Logic paths have different delays
E.g. different output bits in an adder
Delay of signal data dependent
E.g. length of carry
Delay is chip dependent
E.g. Threshold Variation
Delay is environment dependent
E.g. Temperature
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5. Challenge Logic paths have different delays
Delay of signal data dependent
Delay is chip dependent
Delay is environment dependent
Proper behavior depends on inputs being coordinated
Match the inputs that should interact
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6. Accumulator Consider an accumulator based on your 16b adder:
What timing property must hold for this to function correctly?
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7. Accumulator Why don’t we have to worry about:
Result coming out too early? (too fast?)
The accumulation bits change at different times?
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8. Discipline Add circuit elements to
hold values
and change at coordinated point
Control when changes seen by circuit
Only have to make sure to wait long enough for all results
Decouple
timing of signal change
from timing of signal usage
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9. Register Use Where do we commonly use registers in our circuits?
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10. Synchronous Discipline
Add state elements (registers, latches)
Compute
From state elements
Through combinational logic
To new values for state elements
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11. What does this do?
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12. Latch f=0  Out=In f=1  Out=Out f transitions 01 Out holds value
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13. Latch In pass-through mode (f=0), In latch mode (f=1),
acts like buffer
In latch mode (f=1),
holds last value given
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14. Latch In pass-through mode (f=0), In latch mode (f=1),
acts like buffer
In latch mode (f=1),
holds last value given
Ideally: on 01 transition of f snapshots value
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15. Latch In pass-through mode (f=0), In latch mode (f=1),
acts like buffer
In latch mode (f=1),
holds last value given
Ideally: on 01 transition of f snapshots value
What timing relations must hold between In and f for this behavior to occur?
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16. Latch Timing Ideally: on 01 transition of f snapshots value
What timing relations must hold between In and f for this behavior to occur?
Can f transition simultaneous with In?
Can In transition slightly before f ?
Can In transition slightly after f ?
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17. f=0
In=0
Node values?
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18. T=0 both transition to 1 f=01 In=01 Node waveforms (preclass 2)
Example shows a glitch that potentially oscillates
Assuming all nice 0’s and 1’s
Talked about may be degraded values not 0’s and 1’s (may be low pass filtered out).
May or may not oscillate….metastable.
Lots of good nuance and discussion not in slides
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19. In transitions t after f?
What happens to waveform?
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20. In transitions t before f?
What happens to waveform?
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21. Latch Timing
Must present input value sufficiently before the f transitions 01
Must have time to propagate and charge Out
About how long is that in this case?
Setup Time (tsu) – must setup latch input prior to passhold transition
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22. Latch Timing Must not change input before switched over to hold state
How long in this case?
Takes time for inverter to charge
before hold path enabled.
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23. Latch Timing Must not change input before switched over to hold state
Hold Time (thold)– must hold data input until passhold transition complete
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24. Midterm 2 Topics Sizing Logic Tau-model Elmore-delay
Estimation and optimization
Elmore-delay
Energy and power
Dynamic and static
Logic
CMOS
Ratioed
Pass transistor
Regions of operation
Scaling
Noise Margins
No clocking
Except to motivate delay targets and power calculations
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25. What happens here?
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26. Observe Latch alone In flow-through mode half of cycle
Can still get flow-through, combinational cycles
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27. Multiple Latch Discipline
Open latches at disjoint times
At all times: one latch on every path is closed
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28. Register Two back-to-back latches Open one latch at a time
Having one of each on every cycle breaks up combinational cycle
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29. Register Passhold on input latch samples value
Holdpass on output latch presents stored value to circuit
Master and Slave latches
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30. Register How long from f1 fall to output? Part of clkoutput (tclk-q)
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31. What does this do?
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32. What does this do? Outputs when Can ever both be low?
Input 0?
Input 1?
Can ever both be low?
What does output waveform look like?
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33. Clocking Discipline Identify: setup, hold, clk->Q, logic evaluation
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34. Clocking Discipline
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35. Clocking Discipline
Follow discipline of combinational logic broken by registers
Compute
From state elements
Through combinational logic
To new values for state elements
As long as clock cycle long enough,
Will get correct behavior
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36. Ideas Synchronize circuits Leads to clocked circuit discipline
to external events
disciplined reuse of circuitry
Leads to clocked circuit discipline
Uses state holding element
Prevents
Combinational loops
Timing assumptions
(More) complex reasoning about all possible timings
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37. Admin Exam Monday Daylight savings time ends Sunday 2am
No class at noon – office hour
Exam 7—9pm in Towne 309
Daylight savings time ends Sunday 2am
Get an extra hour to study for exam!
Review Sunday 3pm, Ketterer
(make sure you account for time change!)
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