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Ge nMOSFET and pMOSFET Pai-Ying Liao 2018.02.21 (Wed.)

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Presentation on theme: "Ge nMOSFET and pMOSFET Pai-Ying Liao 2018.02.21 (Wed.)"— Presentation transcript:

1 Ge nMOSFET and pMOSFET Pai-Ying Liao (Wed.)

2 First Transistor in 1948 Introduction
Bardeen and coworkers in Bell Labs Good-quality germanium used was produced at Purdue.

3 Why Germanium Introduction Advantages of silicon
Abundant in crust Higher thermal conductivity of 1.50 W/cm·K, compare to Ge W/cm·K Higher bandgap of 1.12 eV at room temperature, compare to Ge 0.66 eV The answer is mobility.

4 Indium Arsenide (InAs)
Introduction Why Germanium (cont.) Mobility of Ge is about three and four times larger than Si for electron and hole, respectively. Germanium (Ge) Silicon (Si) Indium Arsenide (InAs) Unit Bandgap 0.66 1.12 0.35 eV Electron mobility at 300 K 3900 1350 40000 cm2/V·s Hole mobility at 300 K 1900 450 500 Thermal Conductivity 0.58 1.5 0.27 W/cm·K P. D. Ye. Switching Channel, IEEE Spectrum, 2016

5 Ge n(p)FET and CMOS Structure
H. Wu et al. Ge CMOS Technology: Breakthrough of nFETs (Imax=714 mA/mm, gmax=590 mS/mm) by recessed channel and S/D, VLSI 2014 H. Wu et al. First Experimental Demonstration of Ge CMOS Circuit, IEDM 2014

6 Why Recessed S/D/Channel
Performance Why Recessed S/D/Channel H. Wu et al. Ge CMOS Technology: Breakthrough of nFETs (Imax=714 mA/mm, gmax=590 mS/mm) by recessed channel and S/D, VLSI 2014

7 I-V Curves of nFET Performance
H. Wu et al. Ge CMOS Technology: Breakthrough of nFETs (Imax=714 mA/mm, gmax=590 mS/mm) by recessed channel and S/D, VLSI 2014

8 I-V Curves of pFET Performance
H. Wu et al. Deep sub-100nm Ge CMOS Devices on Si with the Recessed S/D and Channel, IEDM 2014

9 Temperature Dependence
Performance Temperature Dependence H. Wu et al. Deep sub-100nm Ge CMOS Devices on Si with the Recessed S/D and Channel, IEDM 2014

10 I-V Curves of CMOS Performance
H. Wu et al. First Experimental Demonstration of Ge CMOS Circuit, IEDM 2014

11 Inverter, NOR, and NAND Logic Ciutcuit
H. Wu et al. First Experimental Demonstration of Ge CMOS Circuit, IEDM 2014

12 Structure Other works H. Wu et al. First Demonstration of Ge 3D FinFET CMOS Circuits, VLSI 2015 H. Wu et al. First Demonstration of Ge Nanowire CMOS Circuits: Lowest SS of 64 mV/dec, Highest gmax of 1057 mS/mm in Ge nFETs and Highest Maximum Voltage Gain of 54 V/V in Ge CMOS Inverters, IEDM 2014


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