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5.5. Fundamentals of low-noise design

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1 5.5. Fundamentals of low-noise design
5. SOURCES OF ERRORS Fundamentals of low-noise design 5.5. Fundamentals of low-noise design hgygygygo

2 5.5.1. Junction-diode noise model
5. SOURCES OF ERRORS Fundamentals of low-noise design Junction-diode noise model Junction-diode noise model ID 1) ID = IS e IS = IF - IS VD /VT 2) idsh2 = 2 q ( IF + IS ) = 2 q ( ID + 2IS )  2 q ID rd idsh ID 3) rd  k T q ID idf idf rd 4) idsh2 = 2 q ID = 2 k T / rd rd ID edsh 5) edsh2 = (2 k T / rd ) rd 2 = 2 k T rd hgygygygo At low frequencies and ID >> IS , idn2 = 2 q ID + Kf ID f , Kf = 2 q ff Note that dynamic resistances do not generate any thermal noise since them dissipate no power, vd id  0.

3 5.5.2. BJT noise model icsh2 = 2 q IC ibsh2 = 2 q IB vbt2 = 4 k T rb
5. SOURCES OF ERRORS Fundamentals of low-noise design BJT noise model BJT noise model C Noiseless rb vbt B icsh ibf ibsh E icsh2 = 2 q IC ibsh2 = 2 q IB vbt2 = 4 k T rb ibf 2 = Kf IB f hgygygygo NB: icf =0  JC < JB, ic=hfeib, (*) ict =0  RC<0.1W, ic=hfeib *Negligible surface effects compared to FETs.

4 vn s(t) = vst(t) + vbt(t) + [ibf (t) + ibsh(t)](RS + rb) + icsh(t)
5. SOURCES OF ERRORS Fundamentals of low-noise design BJT noise model A. Total input noise vs RS rb vbt vbt B ip C hfe ip ic icsh vn s ? rp ro ibf ibsh 1) Total input noise vs. time, vn s(t). vn s(t) = vst(t) + vbt(t) + [ibf (t) + ibsh(t)](RS + rb) + icsh(t) RS+rb+rp hfe hgygygygo 2) Power spectral density of the total input noise, vn s2( f ).

5 vn s(t) = vst(t) + vbt(t) + [ibf (t) + ibsh(t)](RS + rb) + icsh(t)
5. SOURCES OF ERRORS Fundamentals of low-noise design BJT noise model A. Total input noise vn s RS rb vbt vbt B ip C hfe ip ic vs icsh vn s ? rp ro ibf ibsh 1) Total input noise vs. time, vn s(t). vn s(t) = vst(t) + vbt(t) + [ibf (t) + ibsh(t)](RS + rb) + icsh(t) RS+rb+rp hfe hgygygygo 2) Power spectral density of the total input noise, vn s2( f ). vn s2 = 4 k T (rb + RS) + (ibf 2 + ibsh2)(RS + rb)2 + icsh2 RS+rb+rp hfe 2

6 vn s2 = 4 k T (rb + RS) + ibsh2 (RS + rb)2 + icsh2
5. SOURCES OF ERRORS Fundamentals of low-noise design BJT noise model B. Optimum collector current vn s RS rb vbt B ip C hfe ip ic rp ro RS+rb+rp hfe 2 vn s2 = 4 k T (rb + RS) + ibsh2 (RS + rb)2 + icsh2 ibf = 0 hgygygygo vn s2 = 4 k T (rb + RS) + 2 q IC (RS + rb)2 hfe + 2 q IC RS+rb+hfeVT / IC 2 IC opt = hfeVT (1 + hfe )0.5 (RS + rb) Reference: [7]

7 vn s2 = 4 k T (rb + RS) + (ibf 2 + ibsh2)(RS + rb)2 + icsh2
5. SOURCES OF ERRORS Fundamentals of low-noise design BJT noise model C. en- in noise model RS en rb B ip C hfe ip ic vs in rp ro RS+rb+rp hfe 2 vn s2 = 4 k T (rb + RS) + (ibf 2 + ibsh2)(RS + rb)2 + icsh2 hgygygygo en2 = vn s = 4 k T rb + (ibf 2 + ibsh2) rb2 + icsh2 rb+rp hfe 2 RS= 0 in2 = = ibf 2 + ibsh2 + vn s2 RS2 RS=  icsh2 hfe2

8 en2 = 4 k T rb + (ibf 2 + ibsh2) rb2 + icsh2
5. SOURCES OF ERRORS Fundamentals of low-noise design BJT noise model BJT en- in noise model f >> ff rb = 100 W IC = 1 mA hfe = 100 en = 1.36 nV/Hz0.5 in = 1.8 pA/Hz0.5 en / in = 756 W RS = 756 W in RS = 1.4 nV/Hz0.5 C en in B E hgygygygo rb+rp hfe 2 en2 = 4 k T rb + (ibf 2 + ibsh2) rb2 + icsh2 icsh2 hfe2 in2 = ibf 2 + ibsh2 +

9 en = rb 2  1 +  1+hfe in Rs opt =
5. SOURCES OF ERRORS Fundamentals of low-noise design BJT noise model D. Optimum source resistance at IC opt RS en rb B ip C hfe ip ic vs rp ro in en in Rs opt = = rb 2  1 +  1+hfe IC opt IC opt hgygygygo

10 5.4.3. JFET noise model igsh2 = 2 q IG idt2 = 4 k T /(3/2 gm) Kf ID f
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model JFET noise model D Noiseless G idf idt igsh S hgygygygo igsh2 = 2 q IG idt2 = 4 k T /(3/2 gm) Kf ID f idf 2 = NB: idsh = 0

11 Equivalent small-signal model
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model Equivalent small-signal model gmvgs G ig D id vgs rgs ro igsh idf idt hgygygygo

12 Equivalent small-signal model
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model Equivalent small-signal model gmvgs G ig D id vgs vgs rgs ro 1/gm igsh idf idt hgygygygo

13 Equivalent small-signal model
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model Equivalent small-signal model gmvgs G ig D vgs ro ~1/gm igsh idf idt hgygygygo

14 1) Total input noise vs. time, vn s(t).
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model A. Total input noise gmvgs id vs RS G ig D vgs vn s ? ro ~1/gm igsh idf idt 1) Total input noise vs. time, vn s(t). hgygygygo

15 vn s(t) = vst(t) + igsh(t) RS + [idf (t) + idt(t)](1/gm)
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model A. Total input noise vs RS igsh Rs gmvgs G ig D id vn s ? vgs ro ~1/gm igsh idf idt 1) Total input noise vs. time, vn s(t). vn s(t) = vst(t) + igsh(t) RS + [idf (t) + idt(t)](1/gm) hgygygygo

16 vn s(t) = vst(t) + igsh(t) RS + [idf (t) + idt(t)](1/gm)
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model A. Total input noise vn s vs RS igsh Rs gmvgs G ig D id vn s ? vgs ro ~1/gm idf idt 1) Total input noise vs. time, vn s(t). vn s(t) = vst(t) + igsh(t) RS + [idf (t) + idt(t)](1/gm) hgygygygo 2) Power spectral density of the total input noise, vn s2( f ). vn s2 = 4 k T RS + igsh2RS2 + (idf 2+ idt2)/gm2

17 vn s2 = 4 k T RS + igsh2RS2 + (idf 2+ idt2)/gm2
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model B. en- in noise model vn s gmvgs en in RS igsh Rs G ig D id vs vn s ? vgs ro ~1/gm idf idt vn s2 = 4 k T RS + igsh2RS2 + (idf 2+ idt2)/gm2 en2 = vn s = (idf 2+ idt2)/gm2 RS = 0 hgygygygo in2 = = igsh2 vn s2 RS2 RS = 

18 en2 = (idf 2+ idt2)/gm2 in2 = igsh2 BJT JFET en- in noise model
5. SOURCES OF ERRORS Fundamentals of low-noise design JFET noise model BJT JFET en- in noise model f >> ff rb = 100 W IC = 1 mA hfe = 100 en = 1.36 nV/Hz0.5 in = 1.8 pA/Hz0.5 en / in = 756 W RS = 756 W in RS = 1.4 nV/Hz0.5 f >> ff Vp = 2 V IDSS = 10 mA IG = 10 pA en = 1.8 nV/Hz0.5 in = 1.8 fA/Hz0.5 en /in = 1 MW RS = 1 MW in RS = 1.8 nV/Hz0.5 D en in G S hgygygygo en2 = (idf 2+ idt2)/gm2 in2 = igsh2

19 5.5.4. MOSFET noise model idt2 = 4 k T /(3/2 gm) Kf ID f idf 2 =
5. SOURCES OF ERRORS Fundamentals of low-noise design MOSFET noise model MOSFET noise model D Noiseless G idt idf S idt2 = 4 k T /(3/2 gm) idf 2 = Kf ID f hgygygygo NB: igsh = 0 idsh = 0

20 vn s(t) = vst(t) + [idf (t) + idt(t)](1/gm)
5. SOURCES OF ERRORS Fundamentals of low-noise design MOSFET noise model A. Total input noise vn s gmvgs vs RS G D id vn s ? ro 1/gm idf idt 1) Total input noise vs. time, vn s(t). vn s(t) = vst(t) + [idf (t) + idt(t)](1/gm) hgygygygo 2) Power spectral density of the total input noise, vn s2( f ). vn s2 = 4 k T RS + (idf 2+ idt2)/gm2

21 vn s2 = 4 k T RS + (idf 2 + idt2)/gm2
5. SOURCES OF ERRORS Fundamentals of low-noise design MOSFET noise model B. en- in noise model vn s gmvgs en in RS G D id vs ro 1/gm vn s2 = 4 k T RS + (idf 2 + idt2)/gm2 en2 = vn s = (idf 2+ idt2)/gm2 RS = 0 hgygygygo in2 = = 0 vn s2 Rs2 RS = 

22 MOSFET en- in noise model
5. SOURCES OF ERRORS Fundamentals of low-noise design MOSFET noise model JFET MOSFET en- in noise model f >> ff Vp = 2 V IDSS = 10 mA IG = 10 pA en = 1.8 nV/Hz0.5 in = 1.8 fA/Hz0.5 en /in = 1 MW RS = 1 MW in RS = 1.8 nV/Hz0.5 f >> ff Vp = 2 V IDSS = 10 mA en = 1.8 nV/Hz0.5 D en G S en2 = (idf 2+ idt2)/gm2 hgygygygo in = 0

23 5.5.5. Frequency response effect
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect Frequency response effect The aim is to analyze the dependence of a transistor en and in on frequency and the operating point. VCC iC RS vs VBB Cm hgygygygo RS rb vbt vbt B C hfe ip ic vs Cp ip icsh rp ro ibf ibsh

24 ___ ic vs hfe [1/j 2pf (Cp+Cm )]/[rp+1/j 2pf (Cp+Cm )]
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect A. Total input noise Cm RS rb B is C hfe ip ic Cp ip vs rp ro 1) Transconductance gain (icm<< hfe ip) hgygygygo ic vs hfe [1/j 2pf (Cp+Cm )]/[rp+1/j 2pf (Cp+Cm )] RS + rb+ rpII[1/j 2pf (Cp+Cm )] Ag  ___ = ____________________________________ is= 1 hfe /(RS +rb+rp ) 1+j 2pft = _____________ , t = [(RS + rb)IIrp ](Cp+Cm )

25 t = [(RS + rb)IIrp ](Cp+Cm )
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect Cm RS rb vbt vbt B C hfe ip ic vs Cp ip icsh vn s rp ro ibf ibsh hfe /(RS +rb+rp ) 1+j 2pft Ag = _____________ , t = [(RS + rb)IIrp ](Cp+Cm ) 2) Power spectral density of the total input noise, vn s2( f ). hgygygygo RS +rb+rp hfe 2 vn s2 = 4 k T (RS +rb) + (ibf 2 + ibsh2) (RS+rb)2 + icsh2 [1+ (2pft)2]

26 vn s2 = 4 k T (RS +rb) + (ibf 2 + ibsh2) (RS+rb)2 + icsh2 [1+ (2pft)2]
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect RS +rb+rp hfe 2 vn s2 = 4 k T (RS +rb) + (ibf 2 + ibsh2) (RS+rb)2 + icsh2 [1+ (2pft)2] t = [(RS + rb)IIrp ](Cp+Cm ) 3) en and in of the transistor. rb+rp hfe 2 en2 = vn s = 4 k T rb + (ibf 2 + ibsh2) rb2 + icsh2 [1+ (2pften)2] RS = 0 ten = (rbIIrp )(Cp+Cm ) hgygygygo vn s2 RS2 icsh2 hfe2 RS =  in2 = = ibf 2 + ibsh2 + [1+ (2pftin)2] tin = rp (Cp+Cm )

27 en2 = 4 k T rb+ (ibf 2 + ibsh2) rb2 + icsh2 [1+ (2pften)2]
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect B. en- in noise model for high-frequencies Cm RS en in rb B C hfe ip ic vs Cp ip rp ro rb+rp hfe 2 en2 = 4 k T rb+ (ibf 2 + ibsh2) rb2 + icsh2 [1+ (2pften)2] hgygygygo ten = (rbIIrp )(Cp+Cm ) icsh2 hfe2 in2 = ibf 2 + ibsh2 + [1+ (2pftin)2] tin = rp (Cp+Cm )

28 ____ rb+rp 2 hfe en2 = 4 k T rb+ (ibf 2 + ibsh2) rb2 + icsh2
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect C. en( f ) for different IC rb+rp hfe 2 en2 = 4 k T rb+ (ibf 2 + ibsh2) rb2 + icsh2 [1+ (2pften)2] 101 103 105 108 100 102 104 106 109 107 -40 -20 2 4 1 3 5 f, Hz IC opt = 24 mA IC = 0.1 mA en( f ) nV/Hz0.5 hgygygygo rb = 100 W hfe = 100 Cm = 1 pF Cp (1 mA) = 100 pF Ag Ag max dB ____

29 ____ icsh2 hfe2 in2 = ibf 2 + ibsh2 + [1+ (2pftin)2]
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect D. in( f ) for different IC icsh2 hfe2 in2 = ibf 2 + ibsh2 + [1+ (2pftin)2] 2 6 4 8 IC opt = 24 mA IC = 0.1 mA in( f ) pA/Hz0.5 hgygygygo 100 101 102 103 104 105 106 107 108 109 -40 -20 rb = 100 W hfe = 100 Cm = 1 pF Cp (1 mA) = 100 pF Ag Ag max dB ____ 100 101 102 103 104 105 106 107 108 109 f, Hz

30 E. Noise simulation in PSPICE
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect E. Noise simulation in PSPICE V(INOISE)*1G 30 V(ONOISE)*1G/10 20 V(Out1)/V(V1:+)/10 10 hgygygygo 1.0Hz 10KHz 100MHz 1.0THz Frequency

31 5.5.6. Comparison of the BJT, JFET and MOSFET
5. SOURCES OF ERRORS Fundamentals of low-noise design Comparison of the BJT, JFET and MOSFET Comparison of the BJT, JFET and MOSFET rb = 40 W hfe = 500 ro =  IC = 1 mA IDSS = 2 mA Vp = 2 V ID = 1 mA vn s2 = 4 k T RS + igsh2RS2 + (idf 2+ idt2)/gm2 vn s2 = 4 k T (rb + RS) + (ibf 2 + ibsh2)(RS + rb)2 + icsh2 RS+rb+rp hfe 2 vn s2 = 4 k T RS + (idf 2+ idt2)/gm2 hgygygygo

32 5. SOURCES OF ERRORS. 5. 5. Fundamentals of low-noise design. 5. 5. 6
5. SOURCES OF ERRORS Fundamentals of low-noise design Comparison of the BJT, JFET and MOSFET 100 Amplitude spectral density of the total input noise vn s as a function of RS IC opt vn s nV/Hz0.5 5 The 1/f noise is neglected. hgygygygo The JFET gate current is neglected. 1 102 103 104 105 RS, W

33 en at S =  4 kT RS + en 2 + 2r en in + (in RS)2
5. SOURCES OF ERRORS Fundamentals of low-noise design Frequency response effect Example: Comparison of an BJT and JFET in PSPICE RS = 100 W RS = 10 kW hgygygygo en at S =  4 kT RS + en 2 + 2r en in + (in RS)2

34 Conclusion: Guide for selection of the preamplifier
5. SOURCES OF ERRORS Fundamentals of low-noise design Comparison of the BJT, JFET and MOSFET MOSFET Conclusion: Guide for selection of the preamplifier JFET IC amplifiers BJT Transformer coupling hgygygygo 1 10 100 1 k 10 k 100 k 1 M 10 M 100 M 1 G 10 G 100 G Source resistance, RS Reference: [9]

35 5.5.7 Noise analysis of a CE amplifier
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit 5.5.7 Noise analysis of a CE amplifier VCC RC RS vs RE VBB rp io hfe ip ro rb RE RC B E C icsh vs RS ibf ibsh ip vet vbt vst vct ro   hgygygygo

36 Our final aim is to find and minimize the total input noise vn s.
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit Our final aim is to find and minimize the total input noise vn s. rb vbt B C hfe ip ip io icsh rp vst ibf ibsh RS E vet vct vs vn s ? RE RC hgygygygo Let us first find vn s by applying superposition.

37 1+hfe RE/(RE +RS+rb+rp)
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit 1) Signal gain As for vs, vst, vbt, and vet. rb vbt B C hfe ip ip io rp vst RS E vet vs RE RC hgygygygo As  = Gs Gs bs fwd AOL 1+AOLb _______ io vs ___ As = 1 RS+rb+rp+RE ___________ -hfe 1+hfe RE/(RE +RS+rb+rp) ____________________ + 0

38 1+hfe RE/(RE +RS+rb+rp)
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit 2) Noise gain Abf for ibf and ibsh. rb B C hfe ip ip io rp ibf ibsh RS E vs RE RC hgygygygo Abf  = Gbf Gbf bbf fwd AOL 1+AOLb _______ io ibf ___ Abf = RS+rb+RE RS+rb+RE +rp ___________ hfe 1+hfe RE/(RE +RS+rb+rp) ____________________ + 0

39 1+hfe RE/(RE +RS+rb+rp)
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit 3) Noise gain Acsh for icsh. rb B C hfe ip ip io icsh rp RS E vs RE RC hgygygygo Acsh  = Gcsh Gcsh bcsh fwd AOL 1+AOLb _______ io icsh ___ Acsh = RE RE +RS+rb+rp - ___________ hfe 1+hfe RE/(RE +RS+rb+rp) ____________________ - 1

40 ___ ___ io vct Act  = Dct 1 Act = - RC 4) Noise gain Act for vct. rb
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit 4) Noise gain Act for vct. rb B C hfe ip ip rp RS E io vs vct /RC RE RC hgygygygo Act  = Dct io vct ___ Act = - 1 RC ___

41 __________ _______ _____ ________ _____ RSbE = RS +rb+RE
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit 5) Total input noise vs. time, vn s. rb B C hfe ip ip io icsh rp RS ibf ibsh vn s E vs RE RC RSbE = RS +rb+RE hgygygygo vn s(t) = vst +vbt +vet (ibf +ibsh) Abf As __________ + icsh Acsh _______ vct Act _____ vn s2( f ) = 4kT RSbE+(ibf 2+ibsh2) RSbE2 (RSbE+rp)2 hfe2 ________ + icsh2 + 4kT 1 RC As2 _____  0

42 en2 = en s2 = 4 k T RbE + (ibf 2 + ibsh2) RbE 2 + icsh2 (RbE+rp)2 hfe2
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit 6) en- in noise model. en in rb B C hfe ip ic ip rp RC RE E RS E vs (1+hfe) RE RbE = rb + RE hgygygygo en2 = en s2 = 4 k T RbE + (ibf 2 + ibsh2) RbE 2 + icsh2 (RbE+rp)2 hfe2 RS = 0 en s2 RS2 icsh2 hfe2 RS =  in2 = = ibf 2 + ibsh2 +

43 RSbE2 hfe RSbE+hfeVT /IC hfe 2 vn s2 = 4 k T RSbE + 2 q IC + 2 q IC
5. SOURCES OF ERRORS Fundamentals of low-noise design Example circuit 7) Minimizing CE noise. 102 -0.5 -0.4 -0.3 -0.2 -0.1 103 104 en s norm. dB hfe 0.1 0.2 0.4 0.8 1.4 1 10 hfe=104 hfe=102 hfe=103 IC / IC opt en s norm. dB 1.0 0.6 1.2 rb = 100 RS = 200 RE = 200 ibf 2 = 0 vbt2 = 4 k T rb vet2 = 4 k T RE ibsh2 = 2 q IC /b icsh2 = 2 q IC RSbE2 hfe RSbE+hfeVT /IC hfe 2 vn s2 = 4 k T RSbE + 2 q IC + 2 q IC hgygygygo IC opt = hfeVT (1 + hfe )0.5 RSbE vn s min2 = 4 k T RSbE (1 + hfe )0.5 (1 + hfe )0.5-1 Reference: [7]

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