Presentation is loading. Please wait.

Presentation is loading. Please wait.

Introduction to CMOS VLSI Design Chapter 3: CMOS Processing Technology

Published byἌτλας Αποστόλου Modified over 6 years ago

Similar presentations

Presentation on theme: "Introduction to CMOS VLSI Design Chapter 3: CMOS Processing Technology"— Presentation transcript:

1 Introduction to CMOS VLSI Design Chapter 3: CMOS Processing Technology
This work is protected by Canadian copyright laws and is provided solely for the use of instructors in teaching their courses and assessing student learning. Dissemination or sale of any part of this work (including on the Internet) will destroy the integrity of the work and is not permitted. The copyright holder grants permission to instructors who have adopted the textbook accompanying this work to post this material online only if the use of the website is restricted by access codes to students in the instructor's class that is using the textbook and provided the reproduced material bears this copyright notice. slides from David Harris adapted by Duncan Elliott Textbook: CMOS VLSI Design - A Circuits and Design Perspective, 4th Edition, N. H. E. Weste & D. Harris Ch 3 IC Process

2 Ch 3 IC Process

3 Optical Proximity Correction (OPC) Masks
Ch 3 IC Process

4 Ch 3 IC Process

5 Ch 3 IC Process

6 Ch 3 IC Process

7 Ch 3 IC Process

8 Hot Carriers Electric fields across channel impart high energies to some carriers These “hot” carriers may be blasted into the gate oxide where they become trapped Accumulation of charge in oxide causes shift in Vt over time Eventually Vt shifts too far for devices to operate correctly Choose VDD to achieve reasonable product lifetime Worst problems for inverters and NORs with slow input risetime and long propagation delays Use lightly doped drains (LLD) to reduce hot carrier injection (HCI) Ch 3 IC Process

9 Ch 3 IC Process

10 Ch 3 IC Process

11 Local Interconnect Ch 3 IC Process

12 Ch 3 IC Process

13 11 layers of metal [IBM] Ch 3 IC Process

14 Ch 3 IC Process

15 Ch 3 IC Process

16 Ch 3 IC Process

17 Ch 3 IC Process

18 Ch 3 IC Process

19 Ch 3 IC Process

20 Ch 3 IC Process

21 Ch 3 IC Process

22 Ch 3 IC Process

23 Ch 3 IC Process

24 Ch 3 IC Process

25 Ch 3 IC Process

26 Ch 3 IC Process

27 Ch 3 IC Process

28 Ch 3 IC Process

29 Ch 3 IC Process

30 Ch 3 IC Process

31 Ch 3 IC Process

32 Ch 3 IC Process

33 Ch 3 IC Process

34 Ch 3 IC Process

35 Ch7 Robustness & Reliability
Ch 3 IC Process

36 Reliability Hard Errors Soft Errors Ch 3 IC Process

37 Electromigration “Electron wind” causes movement of metal atoms along wires Excessive electromigration leads to open circuits Most significant for unidirectional (DC) current Depends on current density Jdc (current / area) Exponential dependence on temperature Mean Time to Failure (MTTF) Typical limits: Jdc < 1 – 2 mA / mm2 Ch 3 IC Process

38 Self-Heating Current through wire resistance generates heat
Oxide surrounding wires is a thermal insulator Heat tends to build up in wires Hotter wires are more resistive, slower Self-heating limits AC current densities for reliability Typical limits: Jrms < 15 mA / mm2 Ch 3 IC Process

39 Latchup Latchup: positive feedback leading to VDD – GND short
Major problem for 1970’s CMOS processes before it was well understood Avoid by minimizing resistance of body to GND / VDD Use plenty of substrate and well taps Ch 3 IC Process

40 Guard Rings Latchup risk greatest when diffusion-to-substrate diodes could become forward-biased Surround sensitive region with guard ring to collect injected charge Ch 3 IC Process

41 Overvoltage High voltages can damage transistors
Electrostatic discharge Oxide arcing Punchthrough Time-dependent dielectric breakdown (TDDB) Accumulated wear from tunneling currents Requires low VDD for thin oxides and short channels Use ESD protection structures where chip meets real world Ch 3 IC Process

42 Soft Errors In 1970’s, DRAMs were observed to occasionally flip bits for no apparent reason Ultimately linked to alpha particles and cosmic rays Collisions with particles create electron-hole pairs in substrate These carriers are collected on dynamic nodes, disturbing the voltage Minimize soft errors by having plenty of charge on dynamic nodes Tolerate errors through ECC, redundancy Ch 3 IC Process

43 Pitfalls Summary Static CMOS gates are very robust
Will settle to correct value if you wait long enough Other circuits suffer from a variety of pitfalls Tradeoff between performance & robustness Very important to check circuits for pitfalls For large chips, you need an automatic checker. Design rules aren’t worth the paper they are printed on unless you back them up with a tool. Ch 3 IC Process

Download ppt "Introduction to CMOS VLSI Design Chapter 3: CMOS Processing Technology"

Similar presentations

Practical Aspects of Reliability Analysis for IC Designs T. Pompl, C. Schl ü nder, M. Hommel, H. Nielen, J. Schneider.

Practical Aspects of Reliability Analysis for IC Designs T. Pompl, C. Schl ü nder, M. Hommel, H. Nielen, J. Schneider.
Latch-Up and its Prevention Latch is the generation of a low- impedance path in CMOS chips between the power supply and the ground rails due to interaction.

Latch-Up and its Prevention Latch is the generation of a low- impedance path in CMOS chips between the power supply and the ground rails due to interaction.
Lecture 0: Introduction

Lecture 0: Introduction
Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004.

Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004.
Introduction to CMOS VLSI Design Circuit Pitfalls.

Introduction to CMOS VLSI Design Circuit Pitfalls.
Lecture 16: Circuit Pitfalls. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 16: Circuit Pitfalls2 Outline  Variation  Noise Budgets  Reliability  Circuit.

Lecture 16: Circuit Pitfalls. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 16: Circuit Pitfalls2 Outline  Variation  Noise Budgets  Reliability  Circuit.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 20: Circuit Design Pitfalls Prof. Sherief Reda Division of Engineering,

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 20: Circuit Design Pitfalls Prof. Sherief Reda Division of Engineering,
Introduction to CMOS VLSI Design Lecture 0: Introduction

Introduction to CMOS VLSI Design Lecture 0: Introduction
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201- 44494-1. © 2002.

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
Introduction to CMOS VLSI Design Circuit Pitfalls.

Introduction to CMOS VLSI Design Circuit Pitfalls.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201- 44494-1. © 2002.

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
VLSI Digital System Design

VLSI Digital System Design
Design constraints Lection 5

Design constraints Lection 5
Introduction Integrated circuits: many transistors on one chip.

Introduction Integrated circuits: many transistors on one chip.
CSET 4650 Field Programmable Logic Devices

CSET 4650 Field Programmable Logic Devices
Items for Discussion Chip reliability & testing Testing: who/where/what ??? GBTx radiation testing GBTx SEU testing Packaging – Low X0 options, lead free.

Items for Discussion Chip reliability & testing Testing: who/where/what ??? GBTx radiation testing GBTx SEU testing Packaging – Low X0 options, lead free.
Chapter (3) Transistors and Integrated Circuits B I P O L A R J U N C T I O N T R A N S I S T O R BJT in contrast to the unipolar FET Both minority and.

Chapter (3) Transistors and Integrated Circuits B I P O L A R J U N C T I O N T R A N S I S T O R BJT in contrast to the "unipolar" FET Both minority and.
EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.

EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.
Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Similar presentations

Ads by Google