1. Lithography
Advanced

2. Lithography: Advanced
Key parameters:
resolution
alignment (or misalignment)
depth of focus
Resolution:
indicates the smallest feature (or space) that can be produced
One of the limiting factors is wavelength of the light used
26-Nov-18

3. Lithography: Resolution
Resolution and other parameters
Depth of Focus or Depth of Field (DOF)
Details Later
We need small s and large DOF
26-Nov-18

4. Lithography: OPC Resolution Enhancement Techniques (RET)
Optical Proximity Correction
To ‘accommodate’ for diffraction effects
Presence or absence of other features nearby (proximity) will affect the optical behavior
Corrections are made in the layout to account for it (Hence, Optical Proximity Correction or OPC)
Anti Reflective Coating (ARC)
Phase Shift Masks
26-Nov-18

5. Lithography: OPC Resolution Enhancement Techniques (RET)
Optical Proximity Correction
To ‘accommodate’ for diffraction effects
Real
Ideal
Mask
Resist
Presence or absence of neighboring features will alter the width / space of the feature
26-Nov-18

6. Lithography: OPC Resolution Enhancement Techniques (RET) Biasing OPC
Rule based (simple rules, reasonably effective)
Model based (more complicated, computationally intensive, better)
M1 layout
Original
M1 layout
After Bias
26-Nov-18

7. Lithography: OPC Resolution Enhancement Techniques (RET)
Biasing (zoomed picture)
Width is changed (usually increased)
Line End is changed (usually extended) 1
The idea is, after photolithography using mask with structure 2, the resulting structure will be close to what we planned originally (structure 1)
i.e. We try to account for non-idealities in the lithography process 2
26-Nov-18

8. Lithography: OPC Resolution Enhancement Techniques (RET)
Other corrections
A “Tee” may not “print” correctly 3 1
What we want is structure 1
If we make a mask like structure 1, we will end up getting structure 3 2
Hence, we make a plan like structure 2 to obtain on the wafer what we want
Add “dog ears” to the lines
26-Nov-18

9. Lithography: OPC Resolution Enhancement Techniques (RET) Summary 1 2
Layout is OPC’ed
Width bias
This is not the same as enlarging the layout. Here, if width is increased, then space is decreased
Other corrections
To account for non-idealities in the ‘printing’ process
26-Nov-18

10. OPC Example An example from intel web page Wafer (after photo? Drawn /
After etch?)
Drawn /
Pre OPC
Post
OPC
Mask
An example from intel web page

11. OPC vs PPC Other processes (like etch) also have ‘proximity’ effect
Presence or absence of neighbor will affect how a process behaves for a particular feature
Litho ‘neighborhood’ is about 1 um
Etch neighborhood is probably few microns
CMP neighborhood can be few mm (or many microns)
Correcting for optical (litho) and few other processes is called ‘Process proximity correction’ or PPC
Typically litho + etch corrections are used for PPC
CMP corrections are at a different (larger) scale.
Dummy features
26-Nov-18

12. Lithography: ARC RET: Anti Reflective Coating
Reflection ==> Standing waves
ARC Animation
26-Nov-18

13. Lithography: RET RET: Phase Shift Masks (PSM) Normal Masks
OPC can correct only to some extent
When the space and the width are very small (and similar to wavelength of light used)....
Use Phase Shift Mask (PSM)
Amplitude
Intensity X
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14. Lithography: RET RET: Phase Shift Masks (PSM) Normal Mask
Another way to obtain same effect: Etch the glass to different level (schematic in next page)
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15. Lithography: PSM

16. Lithography: RET Review
Optical Proximity Correction
Changes in the layout, mask
Anti Reflective Coating
Change in the process
Phase Shift Mask
Change in the Mask
==> Original layout is first generated
Then modified (to indicate where the change of phase is appropriate)
Computer programs which generate the ‘aerial image’ are used to decide where phase shifting is needed
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17. Lithography: Production
Depth of Focus
Alignment
Partial Field/ Full Field
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18. Lithography: Production
Depth of Focus and Resolution
26-Nov-18

19. Lithography: Production
DOF: Focus Exposure Matrix
DOF: Focus Exposure Matrix
DOF: Focus Exposure Matrix
Exposure is easy to control
Focus: All the parts of chip will NOT be in focus
Plane of focus
Out of focus
DOF in the range of micron
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20. Lithography: Production
DOF: Focus Exposure Matrix
FEM (Focus Exposure Matrix) to obtain process window information
Exposure energy
Likely shorts;
False readings
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21. Lithography: Production
DOF: Focus Exposure Matrix
Remove the false readings (outliers)
Define the focus window
Note: CD here may be SEM CD or ECD
Upper Limit
Lower Limit
Exposure energy
26-Nov-18

22. Lithography: Production
Photo Margin
Depth of focus and exposure margins are very important, particularly in the BEOL
Very little topography in the FEOL ==> usually sufficient photo margin exits
Misalignment
How well can one align to the previous layer?
Should one align to the previous layer or to a standard layer?
Typically a tolerance in the range of +/- 60 nm
26-Nov-18

23. Lithography: Production
Alignment
Statistical Process Control (SPC)
Misalignment measured for example, on 2 wafers in a set of 25 wafers (lot)
In each (of the two) wafers, it may be measured in 5 points (minimum) to perhaps 49 points
Average x misalignment for each wafer is plotted (and similarly y misalignment is plotted)
Each misalignment must be below the absolute spec limit. Average must also be below the upper and lower spec
26-Nov-18

24. Lithography: Production
Alignment
Alignment marks:
Box in box, cross
overlay budget
Statistical Process Control (SPC)
Example data
Misalignment vs run UL
(upper limit) LL
(lower limit)
26-Nov-18

25. Lithography: Production
Partial Fields at the edges of the wafer
Field (one ‘shot’)
Has 9 chips
(for example)
Partial Fields/ Full fields
Partial Field (one ‘shot’)
Has < 9 chips on the wafer
26-Nov-18

26. Lithography: Production
Partial Fields at the edges of the wafer
So what?
Why chips in partial fields?
Use the available space in the wafer
Many processes are ‘pattern dependent’. Uniform pattern makes the process ‘behave’ better. More on this latter
If the partial field regions are left blank, such processes will not give ‘good results’
What is wrong with using chips in the partial field?
26-Nov-18

27. Lithography: Production
Partial Fields at the edges of the wafer
Significant number of chips are in partial fields ( the example in previous page is an exaggeration though)
The chips cannot be just thrown away (working chip == money)
All the partial field chips are in the edge
Majority of processes have center/edge variations and usually the edge chips are affected (partial field and full filed edge chips)
Automatic Focus algorithms are not very effective for partial field
Some of the ‘locations’ in the mask, which are used for determining focus, may fall out of the wafer, in the partial fields
Hence Partial field chips fail more
One solution: Modify algorithm for determining focus at partial fields
Optimize chip placements
Edge exclusion (for many processes)
26-Nov-18

28. Lithography: Production Review
Depth of Focus
Improved by CMP
Alignment
Alignment marks
Partial Field/ Full Field
Tweak focus algorithms
Optimize the field locations to obtain maximum number of ‘good chips’ (which is not always the same as maximum number of chips possible)
26-Nov-18

29. Lithography: Extra What happens for monochromatic vs other light?
Refractive vs Reflective system
Weight/ curvature
Generation
Resolution/ Accuracy
Fiducials - alignment references
Closure checks
Klaris - KLA references
26-Nov-18

30. Lithography: Extra Projection Printing : Mask fabrication (size)
Mask cost
Alignment
Defect size
Higher cost & Maintenance
26-Nov-18

31. Lithography: Extra Modulation Transfer Function (MTF)
M = (Imax-Imin)/ (Imax+Imin)
X-Ray Lithography (parallel)
E Beam Lithography (serial)
X-Ray : 1x mask, non-defect forming
Resist: no effect from x-ray induced photo electrons
Mask: from silicon substrate/ Ta barrier
26-Nov-18