1. SystemC and OO-Synthesis
Greco – Engineering Computation Group Informatics Center - Federal University of Pernambuco
“ A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems”
Remy Eskinazi
Tobias Oppold

2. Scheduling Why RC? RC Challenges Definitions and objectives
Resolution method
TPN Mapping
Design Flow
System Synthesis
Left-Edge allocation of tasks
Simulation results
Conclusions
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RAW 2005

3. Why RC? Low Tooling Cost TTM Non NRE Product Flexibility
Improvement of Paradigm Time x Area
Functional Density
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RAW 2005

4. Some Challenges in RC Scheduling
Area and timing constraints
Better area utilization
Temporal performance
Minimize application time
High Level System Models
Current abstraction is register-level
Formal Methodologies
Performance analysis and optimization
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RAW 2005

5. Definitions and Objectives
Problem Definition
Let A be a hardware application that is composed by the followin elements:
A = (TS, tmax, D), where,
TS = a set of hardware tasks, TS = {T1,T2,T3,…Tn}
tmax = Maxime computational time, tmax  +  {0}
D a set of precedence between tasks, D  TS X TS
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RAW 2005

6. Definitions and Objectives
Problem Definition
The set of tasks TS must be represented in the following form,
TS = {T1,T2,T3,…Tn}, where ech Ti  TS must be represented in the following form,
Ti = {Ri, Ci, Di} where,
Ri = Task releasing time
Ci = Task computational time
Di = Task maxime computational time (Deadline)
11/26/2018
RAW 2005

7. Definitions and Objectives
Execute all tasks that compose A considering the application and architecture constraints
Considering  as the execution time of A we have,
 = Tti + Tr,
where Tti = scheduled tasks computation time and Tr = reconfiguration time
Find the most appropriate sequence for loading the tasks in the reconfigurable architecture () in order minimize  and so obtain
0 = f (E0) = Tti + Tr0
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RAW 2005

8. Resolution Method
1 - Mapping of the application characteristics in a TPN
# of reconfigurable areas
Individual tasks characteristics
Ti = {Ri, Ci, Di}
Tasks precedence
Application Deadline
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RAW 2005

9. Resolution Method
2 – Estructural analysis of the TPN generated, in order to obtain:
A final rechability
State graph for a final marcation
Set the transitions firing sequence in order obtain the minor time elapsed for the final marcation
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RAW 2005

10. State Graph for a final marcation (Covering tree)
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11. TPN Application Mapping
Mapping Models:
Tasks model;
Tasks Precedence model;
Application model
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12. TPN Tasks Model
Let Tmp = (P, T, F, W, m0,  ) be a Timed Petri Net model which represents a particular task Ti where,
P represents a ordered set of places;
T represents a ordered set of transitions;
F  (P X T)  (T X P) represents the edges of the net and the flow relation;
W: F  represents the weigh of the flow relation;
m0: P, represents the initial marking of the net ;
 : T  , is a function that maps each transition to a bounded time delay
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RAW 2005

13. TPN Tasks Model  ti Pa TDi Dti End Process Ti Tt PDi N 11/26/2018
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14. Tasks Precedence Model
Let be Tm1 = (P1, T1, F1, W1, m01, 1 ) and Tm2 = (P2, T2, F2, W2, m02, 2 ) two tasks models.
Tmd = (Pd, Td, Fd, Wd, m0d, d ) = Tm1 [ Tm1 is the resulting Petri Net obtained by the precedence composition between Tm1 and Tm2.
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15. Tasks Precedence Model
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16. TPN Application Model
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17. Design Flow
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18. System Synthesis
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19. System Synthesis Reconfigurable OS O.S. Level 1 (SW) O.S. Level 2 (HW)
Placer
O.S. Bridge
O.S. Level 1
(SW)
Context Manager
Task Deadline Timer
Reconfigurable OS
Task Controller
O.S. Level 2
(HW)
I/O Bridge
Temporary Memory
11/26/2018
RAW 2005

20. System Synthesis Placer Module
Placer (Dispatch)
Deadline Task Timer
Context manager
Placer Module
Initial configuration (initial dispath);
Configure DTT (Deadline Task Timer);
Receive end-task signal;
Check timeout flag;
Save task results in a repository
OS Bridge
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RAW 2005

21. System Synthesis Deadline Tasks Timer (DTT) Module
Placer (Dispatch)
Deadline Task Timer
Context Repository
OS Bridge
Deadline Tasks Timer (DTT) Module
Tasks timing control
Signalizes to placer the tasks deadline
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RAW 2005

22. System Synthesis Context Manager Module Save the tasks contexts;
Placer (Dispatch)
Deadline Task Timer
Context Manager
OS Bridge
Context Manager Module
Save the tasks contexts;
Reboots Context Repository cyclically
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23. System Synthesis OS Bridge Module
Placer (Dispatch)
Deadline Task Timer
Context Manager
OS Bridge
OS Bridge Module
Provides communication between SO level1 e SO level2
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24. Left-Edge Allocation of Tasks
Example: Tasks A through G,
Reconfigurable areas A1, A2, A3
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25. Simulation Results Example: Tasks = Multipliers
Reconfigurable areas A1, A2, A3
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26. Simulation Results
Resulting TPN Model
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27. Simulation Results
Resulting Scheduling for Minimize the application time execution
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28. Simulation Results
Tasks sorting and assigning for reconfigurable slots
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29. Conclusions
We presented an methodology to determinate the static scheduling of hardware tasks using a Timed Petri Net model applicable to reconfigurable FPGAs;
The Methodology seeks minimize the application timing optimizing the tasks scheduling;
The methodology disregards the fragmentation problem in the reconfigurables areas
Future works regards the optimization of reconfigurable areas with the tasks of application
11/26/2018
RAW 2005