1. Review of Aldec Active HDL Implementing Combinational
ECE 448: Lab 1
Review of Aldec Active HDL
Implementing Combinational
Logic in VHDL
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University

2. Introduction to Aldec Active-HDL
Part 1
Introduction to Aldec Active-HDL
Example: MLU

3. MLU Block Diagram A MUX_4_1 NEG_A Y NEG_Y B L1 L0 NEG_B MUX_0 A1 Y11 A1 A
MUX_4_1
IN0 Y1
MUX_1 1
NEG_A
IN1
MUX_2 Y
IN2
OUTPUT
IN3
SEL0
SEL1
NEG_Y 1 B1 B L1 L0
MUX_3
NEG_B

4. Experiment 1
Problem 1
ALU of PicoBlaze

5. PicoBlaze Overview

6. Register File of PicoBlaze1 7
Address
16 Registers
8-bit F s0 s1 s2 s3 s4 s5 s6 s7
Register File of PicoBlaze 2 3 4 5 6 7 sF

7. Condition Code Registers (Flags) and its Definition
Flags are set or reset after ALU operations
Zero flag - Z
zero condition
Z = if result = 0
otherwise
Carry flag - C
overflow, underflow, or various conditions
Example*
C = if result > or
result < 0
otherwise
*Applies only to addition or subtraction related instructions, refer to following slides otherwise

8. Syntax and Terminology
Syntax Example Definition sX kk
PORT(kk)
PORT((sX))
RAM(kk)
s15 14
PORT(2)
PORT((S10))
RAM(4)
Value at register 15
Value 14
Input value from port 2
Input value from port specified by register 10
Value from RAM location 4

9. Addressing modes Immediate mode s2 + 15 + C  s2 ADDCY s2, 15
SUB s7, 7
Direct mode
INPUT s10, 28
ADD s10, s15
PORT(28)  s10
s10 + s15  s10
Indirect mode
INPUT s9, s2
STORE s3, s10
PORT((s2))  s9
s3  RAM((s10))

10. Assembly language vs. machine code
mnemonic [operands]
ADDCY s2, 16
SUB s7, s8
Machine code*
opcode [operands] instruction
1A , A210
1C , C780
*Value in HEX

11. Logic instructions C Z AND IMM, DIR 2. OR 3. XOR IMM, DIR IMM, DIR
AND sX, sY
sX & sY => sX
AND sX, kk
sX & kk => sX
2. OR
OR sX, sY
OR sX, kk
3. XOR
XOR sX, sY
XOR sX, kk
IMM, DIR
IMM, DIR
IMM, DIR

12. Arithmetic Instructions
C Z
Addition
1.1 ADD sX, sY
sX + sY => sX
ADD sX, kk
sX + kk => sX
1.2 ADDCY sX, sY
sX + sY + CARRY => sX
ADDCY sX, kk
sX + kk + CARRY => sX
2. Subtraction
2.1 SUB sX, sY
sX - sY => sX
SUB sX, kk
sX - kk => sX
2.2 SUBCY sX, sY
sX - sY - CARRY => sX
SUBCY sX, kk
sX - kk - CARRY => sX
IMM, DIR
IMM, DIR

13. Test and Compare Instructions
C Z
TEST
TEST sX, sY
sX & sY => none
TEST sX, kk
sX & kk => none
COMPARE
COMPARE sX, sY
sX – sY => none
COMPARE sX, kk
sX – kk => none
IMM, DIR
IMM, DIR

14. Data Movement Instructions (1)
C Z
- -
LOAD
LOAD sX, sY
sY => sX
LOAD sX, kk
kk => sX
STORE
STORE sX, PP
sX => RAM(PP)
STORE sX, (sY)
sX => RAM((sY))
FETCH
FETCH sX, PP
RAM(PP) => sX
FETCH sX, (sY)
RAM((sY)) => sX
IMM, DIR
- -
DIR, IND
- -
DIR, IND

15. Data Movement Instructions (2)
C Z
- -
INPUT
INPUT sX, PP
sY => PORT(PP)
INPUT sX, (sY)
sX => PORT((sY))
OUTPUT
OUTPUT sX, PP
PORT(PP) => sX
OUTPUT sX, (sY)
PORT((sY)) => sX
DIR, IND
- -
DIR, IND

16. Edit instructions - Shifts
*All shift instructions affect Zero and Carry flags

17. Edit instructions - Rotations
*All rotate instructions affect Zero and Carry flags

18. PicoBlaze ALU Instruction Set Summary (1)17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ADD sX, kk x y
ADD sX, sY k
ADDCY sX, kk
ADDCY sX, sY
AND sX, kk
AND sX, sY
COMPARE sX, kk
COMPARE sX, sY
FETCH sX, ss s
FETCH sX, (sY)
INPUT sX, (sY)
INPUT sX, PP p
LOAD sX, kk
LOAD sX, sY
OR sX, kk
OR sX, sY
OUTPUT sX, (sY)
OUTPUT sX, PP

19. PicoBlaze ALU Instruction Set Summary (2)17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RL sX x
RR sX
SL0 sX
SL1 sX
SLA sX
SLX sX
SR0 sX
SR1 sX
SRA sX
SRX sX
STORE sX, ss s
STORE sX, (sY) y
SUB sX, kk k
SUB sX, sY
SUBCY sX, kk
SUBCY sX, sY
TEST sX, kk
TEST sX, sY
XOR sX, kk
XOR sX, sY

20. Part 2
Mini ALU

21. opcode 4 4 A 4 4
Mini ALU R B 4 M

22. Mnemonic
Operation
Opcode
ADDAB
R= A + B
0000
ADDAM
R = A + M
0001
SUBAB
R = A - B
0010
SUBAM
R = A - M
0011
NOTA
R = NOT A
0100
NOTB
R = NOT B
0101
NOTM
R = NOT M
0110
ANDAB
R = A AND B
0111
ANDAM
R = A AND M
1000
ORAB
R = A OR B
1001
ORAM
R = A OR M
1010
XORAB
R = A XOR B
1011
XORAM
R = A XOR M
1100

23. Block diagram

24. Example 3
Variable Rotator

25. C = A <<< B Function A – 4-bit data input
B – 2-bit rotation amount

26. Interface A 4 2 B 4 C

27. Block diagram C

28. Fixed Shifts in VHDL A_shiftR <= ‘0’ & A(3 downto 1); A>>1
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.
‘0’
A(3)
A(2)
A(1)
A_shiftR <= ‘0’ & A(3 downto 1);

29. Arithmetic Functions in VHDL (1)
To use arithmetic operations involving
std_logic_vectors you need to include the
following library packages:
library ieee;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.ALL;
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.

30. Arithmetic Functions in VHDL (2)
You can use standard +, - operators
to perform addition and subtraction:
signal A : STD_LOGIC_VECTOR(3 downto 0);
signal B : STD_LOGIC_VECTOR(3 downto 0);
signal C : STD_LOGIC_VECTOR(3 downto 0); ……
C<= A + B;
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.