1. Mano and Kime Sections 7-6 – 7-8
ALU and Shifters Lab 2
Mano and Kime
Sections 7-6 – 7-8

2. ALU and Shifters
ALUs
Shifters
Lab 2

3. n-Bit ALU

4. Arithmetic Circuit

10. ALU and Shifters
ALUs
Shifters
Lab 2

11. 4-Bit Basic Shifter S = 00 No shift S = 01 Right shift
S = 10 Left shift

12. 4-Bit Barrel
Shifter

13. ALU and Shifters
ALUs
Shifters
Lab 2

14. Lab 2 – ALU1 Shifting, Increment and Decrement Instructions
sel y
Instruction name
“000”
a + 1 1+
“001”
a - 1 1-
“010”
not a
invert
“011”
shift left a 2*
“100”
logic shift right a
U2/
“101”
arithmetic shift right a 2/
“110”
all ones
true
“111”
all zeros
false

15. alu1 entity library IEEE; use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu1 is
generic(width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC_VECTOR(2 downto 0);
y: out STD_LOGIC_VECTOR(width-1 downto 0) );
end alu1;

16. Note for…loop architecture alu1_arch of alu1 is begin
alu_1: process(a, sel)
variable true, false: STD_LOGIC_VECTOR (width-1 downto 0);
-- true is all ones; false is all zeros
for i in 0 to width-1 loop
true(i) := '1';
false(i) := '0';
end loop;
case sel is
when "000" =>
y <= a + 1;
when "001" =>
y <= a - 1;
when "010" => invert
y <= not a;
when "011" => *
y <= a(width-2 downto 0) & '0';
when "100" => U2/
y <= '0' & a(width-1 downto 1);
when "101" => /
y <= a(width-1) & a(width-1 downto 1);
when "110" => TRUE
y <= true;
when others => FALSE
y <= false;
end case;
end process alu_1;
end alu1_arch;
Note for…loop