1. EE 445S Real-Time Digital Signal Processing Lab Spring 2014
Lab #1.1 Review of Concepts in Computer Architecture
Prepared by: Zeina Sinno 1

2. Outline Some Concepts in Computer Architecture
Fixed Point Number – Floating Point Number
Cache
Register
Pipelining
Present hardware then software 2 2

3. Fixed Point Number
A fixed-point number representation is a real data type for a number that has a fixed number of digits after (and sometimes also before) the radix point. 
Fixed-point numbers are useful for representing fractional values, usually in base 2 or base 10.
Fixed points are used when the executing processor has no floating point unit (FPU) or in case the fixed-point provides improved performance or accuracy.
Most low-cost embedded microprocessors and microcontrollers do not have a floating point unit. 3 3

4. Fixed Point Number
A value of a fixed-point data type is essentially an integer that is scaled by a specific factor determined by the type.
For example, the value 1.23 can be represented as 1230 in a fixed-point data type with scaling factor of 1/1000, and the value 1,230,000 can be represented as 1230 with a scaling factor of 1000.
Because fixed point operations can produce results that have more bits than the operands, there is possibility for information loss.
For instance, the result of fixed point multiplication could potentially have as many bits as the sum of the number of bits in the two operands. 4 4

5. Fixed Point Number
Multiplying two fixed point numbers with I integer bits and Q fractional bits produces a number that might have up to 2I integer bits and 2Q fractional bits.
In order to fit the result into the same number of bits as the operands, the answer must be rounded or truncated. The choice of which bits to keep is very important. 5 5

6. Floating Point Number 6 6

7. IEEE Standard for Floating Point Representation
The standard provides for many closely related formats, differing in only a few details.
Two among the widely used formats are:
Single precision: usually used to represent the "float" type in the C language family. This is a binary format that occupies 32 bits, its significand has a precision of 24 bits and 1 bit is assigned for the sign of the number.
Double precision, usually used to represent the "double" type in the C language family. This is a binary format that occupies 64 bits, its significand has a precision of 53 bits and 1 bit is assigned for the sign of the number. 7 7

8. Cache
Accessing the main memory to get the value of an operand is an expensive operation.
Assuming that the operand accessed is needed frequently one way to increase the efficiency would be by storing a copy of the value of this operand in some memory in the CPU. This is in fact the cache.
The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere. 8 8

9. Cache
If requested data is contained in the cache (cache hit), this request can be served by simply reading the cache, which is comparatively faster.
Otherwise (cache miss), the data has to be recomputed or fetched from its original storage location, which is comparatively slower. . 9 9

10. Register
A register is a small amount of storage available as a part of the CPU or other digital processor.
For a load store architecture, the data is loaded from the main memory into registers in order to be able to execute on it arithmetic operations, manipulate it… Then it is stored back in the main memory.
Registers are either user accessible or not. In the latter case, these registers cannot be accessed by the instructions, and are referred as internal registers.
User accessible registers include data registers and address registers.
Internal registers include instruction registers. 10 10

11. Pipelining CPU operations Overlap operations to increase performance
Fetch instruction from (on-chip) program memory
Decode instruction
Execute instruction including reading data values
Overlap operations to increase performance
Pipeline CPU operations to increase clock speed over a sequential implementation
Separate parallel functional units
Peripheral interfaces for I/O do not burden CPU

12. Pipelining Sequential (Motorola)56000)
Fetch
Decode
Read
Execute
Pipelined (Most conventional DSP processors)
Fetch
Decode
Read
Execute
Superscalar (Pentium, MIPS)
Managing Pipelines
compiler or programmer (TMS320C6000)
pipeline interlocking in processor (TMS320C30)
hardware instruction scheduling
Fetch
Decode
Read
Execute
Superpipelined (TMS320C6000)
Fetch
Decode
Execute