1. EECS 150 - Components and Design Techniques for Digital Systems Lec 07 – PLAs and FSMs 9/21-04
David Culler
Electrical Engineering and Computer Sciences
University of California, Berkeley
9/21/04
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2. Review: minimum sum-of-products expression from a Karnaugh map
Step 1: choose an element of the ON-set
Step 2: find "maximal" groupings of 1s and Xs adjacent to that element
consider top/bottom row, left/right column, and corner adjacencies
this forms prime implicants (number of elements always a power of 2)
Repeat Steps 1 and 2 to find all prime implicants
Step 3: revisit the 1s in the K-map
if covered by single prime implicant, it is essential, and participates in final cover
1s covered by essential prime implicant do not need to be revisited
Step 4: if there remain 1s not covered by essential prime implicants
select the smallest number of prime implicants that cover the remaining 1s
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3. Big Idea: boolean functions <> gates
22^n boolean functions of n inputs
Each represented uniquely by a Truth Table
Describes the mapping of inputs to outputs
Each boolean function represented by many boolean expressions
Axioms establish equivalence
Transform expressions to optimize
Each boolean expression has many implementations in logic gates
Canonical: Sum of Products, Product of Sums
Minimal
K-maps as a systematic means of reducing Sum of Products
Any acyclic network of gates implements a boolean function
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4. Outline Programmable Logic to Implement Sum of Products
Designing with PLAs
Announcements
FSM Concept
Example: history sensitive computation
Example: Combo lock
Encodings and implementations
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5. How to quickly implement SofPs?
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6. One Answer: Xilinx 4000 CLB
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7. Two 4-input functions, registered output
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8. 5-input function, combinational output
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9. Programmable Logic Regular logic
Programmable Logic Arrays
Multiplexers/Decoders
ROMs
Field Programmable Gate Arrays (FPGAs)
Xilinx
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10. Programmable Logic Arrays (PLAs)
Pre-fabricated building block of many AND/OR gates
Actually NOR or NAND
”Personalized" by making or breaking connections among gates
Programmable array block diagram for sum of products form
• • •
inputs
AND array
• • •
outputs
OR array
product terms
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11. Shared Product Terms F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B
example:
input side:
personality matrix
1 = uncomplemented in term
0 = complemented in term
– = does not participate
product inputs outputs
term A B C F0 F1 F2 F3 AB 1 1 – B'C – AC' 1 – B'C' – A 1 – –
output side:
reuse of terms
1 = term connected to output
0 = no connection to output
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12. Before Programming
All possible connections available before "programming"
In reality, all AND and OR gates are NANDs
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13. After Programming Unwanted connections are "blown"
Fuse (normally connected, break unwanted ones)
Anti-fuse (normally disconnected, make wanted connections) A B C F1 F2 F3 F0 AB
B'C
AC'
B'C'
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14. Alternate Representation for High Fan-in Structures
Short-hand notation--don't have to draw all the wires
Signifies a connection is present and perpendicular signal is an input to gate
notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D A B C D AB
AB+A'B'
A'B'
CD'
CD'+C'D
C'D
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15. Programmable Logic Array Example
Multiple functions of A, B, C
F1 = A B C
F2 = A + B + C
F3 = A' B' C'
F4 = A' + B' + C'
F5 = A xor B xor C
F6 = A xnor B xnor C
full decoder as for memory address
bits stored in memory
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC A B C F1 F2 F3 F4 F5 F6
A B C F1 F2 F3 F4 F5 F6
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16. PLAs Design Example BCD to Gray code converter
A B C D W X Y Z – – – – – 1 1 – – – – – –
X 1
X X X
X X D A B C
X 0
X X X
X X D A B C
K-map for W
K-map for X
X 0
X X X
X X D A B C
X 1
X X X
X X D A B C
minimized functions:
W = A + B D + B C
X = B C'
Y = B + C
Z = A'B'C'D + B C D + A D' + B' C D'
K-map for Y
K-map for Z
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17. PLAs Design Example (cont’d)
Code converter: programmed PLA
minimized functions:
W = A + B D + B C
X = B C'
Y = B + C
Z = A'B'C'D + B C D + A D' + B' C D'
A B C D
W X Y Z A BD BC
BC' B C
A'B'C'D
BCD
AD'
BCD'
not a particularly good
candidate for PLA
implementation since no terms are shared among outputs
however, much more compact and regular implementation when compared with discrete AND and OR gates
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18. PLAs Design Example (revisited)
BCD to Gray code converter
A B C D W X Y Z – – – – – 1 1 – – – – – – A A
X 1
X X X
X X
X 0
X X X
X X D D C C B B
K-map for W
K-map for X A A
X 0
X X X
X X
X 1
X X X
X X
minimized functions:
W =
X =
Y =
Z = D D C C B B
K-map for Y
K-map for Z
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19. PLAs Design Example BCD to Gray code converter BC’
A B C D W X Y Z – – – – – 1 1 – – – – – – A A
X 1
X X X
X X
X 0
X X X
X X D D C C B B
K-map for W
K-map for X
BC’ A A
X 0
X X X
X X
X 1
X X X
X X
minimized functions:
W =
X =
Y =
Z = D D C C B B
K-map for Y
K-map for Z
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20. PLA Second Design Example
Magnitude comparator
EQ NE LT GT
A'B'C'D'
A'BC'D
ABCD
AB'CD'
AC'
A'C
B'D
BD'
A'B'D
B'CD
ABC
BC'D'
A B C D D A B C D A B C
K-map for EQ
K-map for NE D A B C D A B C
K-map for LT
K-map for GT
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21. Other Options Muxes DeMuxes ROMs LUTs We will return to these later
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22. Announcements Reading: Katz 1.4.2 (again), 7.1-3, pp 174-186
Mid term th 10/7
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23. Recall: What makes Digital Systems tick?
Combinational
Logic
clk
time
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24. Recall 61C: Single-Cycle MIPS17
reg[1] 3 1 x
LW r3, 17(r1)
ALU
reg[1]+17
instruction
memory PC
registers
memory
Data
MEM[r1+17] +4
imm
1. Instruction
Fetch
2. Register
Read
3. Execute
4. Memory
5. Reg.
Write
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25. Recall 61C: 5-cycle Datapath - pipelineIR
5. Reg.
Write 17
reg[1]
2. Register
Read 3 1 x
LW r3, 17(r1)
1. Instruction
Fetch
ALU
reg[1]+17
3. Execute
instruction
memory PC
registers
memory
Data
MEM[r1+17]
4. Memory +4
imm
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26. Typical Controller: state
Next state i2 i1 i0 o2 o1 o0 1
state
Combinational
Logic
Example: Gray Code
Sequence
state(t+1) = F ( state(t) )
000
001
011
010
110
111
101
100
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27. Typical Controller: state + output
Output (t) = G( state(t) )
state
Next state i2 i1 i0 o2 o1 o0 1 1
odd
state
Combinational
Logic
state(t+1) = F ( state(t) )
000/0
001/1
011/0
010/1
110/0
111/1
101/0
100/1
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28. Typical Controller: state + output + input
Output (t) = G( state(t) )
state
Next state i2 i1 i0 o2 o1 o0 1
x x x
clr 1
odd
Input
state
Combinational
Logic
state(t+1) = F ( state(t), input (t) )
clr=1
000/0
001/1
011/0
010/1
110/0
111/1
101/0
100/1
clr=0
clr=?
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29. Two Kinds of FSMs Moore Machine vs Mealy Machine
Output (t) =
G( state(t), Input )
Output (t) = G( state(t))
Input
Input
state
state
Combinational
Logic
state(t+1) = F ( state(t), input(t))
state(t+1) = F ( state(t), input)
Input / Out
Input
State
State / out
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30. Parity Checker Example
A string of bits has “even parity” if the number of 1’s in the string is even.
Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even and outputs a 1 if odd:
Can you guess a circuit that performs this function?
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31. Formal Design Process “State Transition Diagram”
circuit is in one of two states.
transition on each cycle with each new input, over exactly one arc (edge).
Output depends on which state the circuit is in.
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32. Formal Design Process State Transition Table:
Invent a code to represent states:
Let 0 = EVEN state, 1 = ODD state
present next
state OUT IN state
EVEN EVEN
EVEN ODD
ODD ODD
ODD EVEN
present state (ps) OUT IN next state (ns)
Derive logic equations from table (how?):
OUT = PS
NS = PS xor IN
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33. Formal Design Process Review of Design Steps:
Logic equations from table:
OUT = PS
NS = PS xor IN
Review of Design Steps:
1. Circuit functional specification
2. State Transition Diagram
3. Symbolic State Transition Table
4. Encoded State Transition Table
5. Derive Logic Equations
6. Circuit Diagram
FFs for state
CL for NS and OUT
Circuit Diagram:
XOR gate for ns calculation
DFF to hold present state
no logic needed for output ns ps
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34. Finite State Machines (FSMs)
FSM circuits are a type of sequential circuit:
output depends on present and past inputs
effect of past inputs is represented by the current state
Behavior is represented by State Transition Diagram:
traverse one edge per clock cycle.
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35. FSM Implementation FFs form state register
number of states  2number of flip-flops
CL (combinational logic) calculates next state and output
Remember: The FSM follows exactly one edge per cycle.
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36. Another example Door combination lock:
punch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset
inputs: sequence of input values, reset
outputs: door open/close
memory: must remember combination or always have it available as an input
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37. Implementation in software
integer combination_lock ( ) {
integer v1, v2, v3;
integer error = 0;
static integer c[3] = 3, 4, 2;
while (!new_value( ));
v1 = read_value( );
if (v1 != c[1]) then error = 1;
v2 = read_value( );
if (v2 != c[2]) then error = 1;
v3 = read_value( );
if (v2 != c[3]) then error = 1;
if (error == 1) then return(0); else return (1); }
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38. Implementation as a sequential digital system
Encoding:
how many bits per input value?
how many values in sequence?
how do we know a new input value is entered?
how do we represent the states of the system?
Behavior:
clock wire tells us when it’s ok to look at inputs (i.e., they have settled after change)
sequential: sequence of values must be entered
sequential: remember if an error occurred
finite-state specification
reset
value
open/closed
new
clock
state
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39. Sequential example: abstract control
Finite-state diagram
States: 5 states
represent point in execution of machine
each state has outputs
Transitions: 6 from state to state, 5 self transitions, 1 global
changes of state occur when clock says it’s ok
based on value of inputs
Inputs: reset, new, results of comparisons
Output: open/closed
ERR
closed
C1!=value & new
C2!=value & new
C3!=value & new S1 S2 S3
OPEN
reset
closed
closed
closed
open
C1=value & new
C2=value & new
C3=value & new
not new
not new
not new
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40. data-path vs. control Internal structure data-path
storage for combination
comparators
control
finite-state machine controller
control for data-path
state changes controlled by clock
new
equal
reset
value C1 C2 C3
mux control
multiplexer
controller
clock
comparator
equal
datapath
open/closed
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41. Sequential example (cont’d): finite-state machine
refine state diagram to include internal structure
closed
mux=C1
reset
equal & new
not equal & new
not new S1 S2 S3
OPEN
ERR
mux=C2
mux=C3
open
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42. Sequential example (cont’d): finite-state machine
generate state table (much like a truth-table)
closed
mux=C1
reset
equal & new
not equal & new
not new S1 S2 S3
OPEN
ERR
mux=C2
mux=C3
open
Symbolic states
reset new equal state state mux open/closed 1 – – – S1 C1 closed 0 0 – S1 S1 C1 closed S1 ERR – closed S1 S2 C2 closed 0 0 – S2 S2 C2 closed S2 ERR – closed S2 S3 C3 closed 0 0 – S3 S3 C3 closed S3 ERR – closed S3 OPEN – closed 0 – – OPEN OPEN – open 0 – – ERR ERR – closed
next
Encoding?
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43. Sequential example: encoding
Encode state table
state can be: S1, S2, S3, OPEN, or ERR
needs at least 3 bits to encode: 000, 001, 010, 011, 100
and as many as 5: 00001, 00010, 00100, 01000, 10000
choose 4 bits: 0001, 0010, 0100, 1000, 0000
Encode outputs
output mux can be: C1, C2, or C3
needs 2 to 3 bits to encode
choose 3 bits: 001, 010, 100
output open/closed can be: open or closed
needs 1 or 2 bits to encode
choose 1 bits: 1, 0
binary
One-hot
hybrid
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44. Sequential example (cont’d): encoding
Encode state table
state can be: S1, S2, S3, OPEN, or ERR
choose 4 bits: 0001, 0010, 0100, 1000, 0000
output mux can be: C1, C2, or C3
choose 3 bits: 001, 010, 100
output open/closed can be: open or closed
choose 1 bits: 1, 0
reset new equal state state mux open/closed 1 – – – – – – – – – – – – – – – – 0
next
good choice of encoding!
mux is identical to last 3 bits of next state open/closed is identical to first bit of state
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45. Sequential example (cont’d): controller implementation
Implementation of the controller
special circuit element, called a register, for remembering inputs
when told to by clock
new
equal
reset
mux control
controller
clock
new
equal
reset
open/closed
mux control
comb. logic
clock
state
open/closed
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46. One-hot encoded FSM Even Parity Checker Circuit: In General:
FFs must be initialized for correct operation (only one 1)
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47. FSM Implementation Notes
General FSM form:
All examples so far generate output based only on the present state:
Commonly called Moore Machine
(If output functions include both present state and input then called a Mealy Machine)
Often PLAs
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48. Design hierarchy system data-path control code registers
state registers
combinational logic
multiplexer
comparator
register
logic
switching networks
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