1. 8051 Timers / Counters It has two timers Timer 0 and Timer 1.
The timers are 16- bit registers.
Since 8051 is 8 – bit microcontroller, each 16 – bit register can be accessed as low – byte register (TL) and high – byte register (TH).
These registers are accessed like other registers (A, B, R0, R1 etc.) in 8051

2. Timer Control (TCON) Register Time Mode (TMOD) Register
Timer 1 Register
Timer 0 Register
TH1
(8 – bit)
TL1
TH0
(8 – bit)
TL0
Timer Control (TCON) Register
Time Mode (TMOD) Register
Timer Register

3. Structure of TMOD Register
Timer / counter mode control (TMOD) is the special function register in 8051 having the following format:
LSB
MSB
Timer 0
Timer 1
TMOD Register
GATE
C / T M1 M0

4. TMOD Register Responsibility
Select Timer 0 to operate as a counter or timer.
Select Timer 1 to operate as a counter or timer.
Select the mode in which timer should operate.
M1, M0 : These bits select the timer mode. There are four modes of timer, mode 0, mode 1, mode 2, and mode 3.

5. 8 – bit timer / counter “THx” with TLx” s 5 – bit prescaler
Operating Mode
8 – bit timer / counter “THx” with TLx” s 5 – bit prescaler 1
16 – bit Timer / Counter “THx” with “TLx” are cascaded; there is no prescaler.
8 – bit auto – reload Timer / Counter “Thx” holds a value which is to be reloaded into “TLx”, each time it overflows.
(Timer 0) TL0 is an 8 – bit Timer / Counter controlled by the standard Timer 0 control bits. TH0 is an 8 – bit timer only controlled by Timer 1 control bits.
(Timer 1) Timer / Counter 1 Stopped.
C / T : This bit is cleared (C / T = 0) for selecting “Timer” operation and is set (C/ T=1) for selecting “Counter Operation).
GATE : Gating control when set. Timer / Counter “x” is enabled only while “INTx” pin is high and “TRx” control bit is set. When cleared Timer “x” is enabled whenever “TRx” control bit is set.

6. Structure of TCON Register
MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON Register

7. TCON – Timer / Counter Control / Status register
Symbol
Position
Name and Significance
TF1
TCON.7
Timer 1 overflow flag. Set by Hardware on timer / counter overflow. Cleared when interrupt processed.
TR1
TCON.6
Timer 1 Run control bit. Set / Cleared by software to turn timer / counter on / off
TF0
TCON.5
Timer 0 overflow flag. Set by hardware on timer / counter overflow. Cleared when interrupt is processed.
TRO
TCON.4
Timer 0 Run control bit. Set / Cleared by software to turn timer / counter on / off.
IE1
TCON.3
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.
IT1
TCON.2
Interrupt 1 Type control bit. Set / Cleared by software to specify falling edge / low level triggered external interrupts.
IE0
TCON.1
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.
IT0
TCON.0
Interrupt 0 Type control bit. Set / Cleared by software to specify falling edge / low level triggered external interrupts.
TCON – Timer / Counter Control / Status register

8. TCON Register Operations
Start and Stop timer 0 and timer 1.
It provides status of timer / counter overflows.
It provides status of external interrupts.
It configures external interrupts as either low level triggered or falling edge triggered.