1. Post-CMOS Grand Challenges
Juri Matisoo
Vice-President, Technology
Semiconductor Industry Association

2. Acknowledgements SIA TSC Working Group Bob Doering, TI, Chair;
George Bourianoff, Intel
Philip Wong, IBM
Luan Tran, Micron
Papu Maniar, Motorola
Jim Hutchby, SRC

3. Agenda/Overview
Value and Need for Investment in Nanoelectronics* Research
Long-Term Manufacturing Research
Long-Term Device Research
Recommendations Summary
* In this presentation: “nanoelectronics” ≡ “future IC technology”

4. Benefits to the U.S. from the Semiconductor Industry
Powers other Industries
Spurs Economic Growth
~3% of GDP growth due to “computer quality” increase
Creates High-Wage Jobs
~300K jobs in the U.S. currently
Fosters International Competitive Advantage
Bolsters National Defense/Homeland Security
Intelligence gathering/processing
Guidance/Control systems (e.g., for E2C2)
Logistics management/efficiency
Communications Technology

5. The Need for New Enablers of Progress in Future ICs
The industry productivity gains of 25%/year reduction in cost/function and improved performance and reduced power consumption over the last 40 years have been driven by miniaturization of semiconductor devices.
The International Technology Roadmap for Semiconductors (ITRS) predicts that over the next years, this trend will end.
New devices and manufacturing techniques are needed.

6. Long-Range Grand Challenges
In the long term, the SIA TSC feels that we face two grand challenges worthy of very large federal funding:
Scaling limits of “evolutionary lithography/thin-film manufacturing”
Scaling limits of “charge-transport devices/interconnect”
We suggest that these might be overcome through new and synergistic research in the under-funded broad areas of:
“Directed self-assembly” of complex structures with “nanoelectronics-functionality” (computation, comm., etc.)
“Beyond (classical) charge transport” signal-processing/ computational technology (e.g., based on quantum-states)

7. Rationale for Directed Self-Assembly
Break the manufacturing “scaling tyranny” of:
Maintaining adequate process-control margin
Contamination-density-limited yield
Escalating wafer-fab capital cost
Lengthening production cycle time
Rapidly increasing photomask cost

8. Desired Consequences of Directed Self-Assembly
Approaching “atomic-level” perfection/control in manufacturing of nano-systems (“future SOCs”)
Providing radically enhanced and affordable functionality in nano-systems
Revolutionizing fab economics and logistics
Application to a broad range of devices (e.g., from “ultimate CMOS” to “quantum-state”)
Note: the principal barrier to implementation of advanced device concepts is often “manufacturing feasibility”

9. Current Examples of Self-Assembly Techniques

10. The Self-Assembly “Place and Route” Problem

13. IC Metrics that Should Guide Research on NanoManufacturing
Cost/Integrated-Function (e.g., $/gate or $/bit integrated into system)
Operations/Second (computation speed, e.g. MIPS)
Power Dissipation (both operating and standby power)
Integration Density (e.g., integrated functions/cm2 or /cm3)
Integration Diversity (SOC functions - e.g., analog, RF, e-RAM)
Capital Cost/Capacity (e.g., capital investment $/chips/month)
Mfg. Cycle Time (impacts time-to-market and ASIC delivery)
R&D Cost (e.g., cost per new product or tech node)
NanoManufacturing Goals: 100x beyond limits of the evolutionary approach

14. Rationale for Beyond-Charge-Transport Signal-Processing/Computation
Break the “CMOS electrical scaling tyranny,” e.g.:
Voltage (limiting speed/power/error-rate tradeoff)
Resistance (limiting speed and low power)
Capacitance (limiting speed and low active power)
Charge-Leakage Mechanisms (limiting standby power)

15. Desired Consequences of Beyond-Charge-Transport Computation/Signal-Processing
Providing significant performance improvements via mechanisms beyond merely scaling physical dimensions (e.g., multiple logic states, far-from- equilibrium operation)
Providing qualitatively new types of nano-system functionality (e.g., direct sensing/actuating)

16. Some Potential State Variables Alternative to Classical Electric Charge
Atomic/molecular quantum states (including “artificial atoms”)
Magnetic-dipole magnitude/orientation (e.g., electron/nuclear spin)
Electric-dipole magnitude/orientation
Magnetic flux quanta
Photon number
Photon polarization
Mechanical state

17. Example: Spin-Resonance Transistor (SRT)
Transistors that control spins rather than charge
More energy efficient than conventional transistors
Combines magnetic and electrostatic fields
May enable quantum computing
Binary information can be represented by the spin of a single dopant atom bound to lattice site in a semiconducting material.
Changing the bit involves flipping the spin from spin up to spin down of visa versa.
The SRT shown above is designed to set, sense and manipulate the spins of two individual phosphorous atoms.
The graded SiGe alloy has an atomic g factor that varies with the relative abundances of Si and Ge.
The g factor determines the frequency of atomic precession in an applied magnetic field. In particular, it controls whether or not the precessional frequency is resonant with the precession. When a resonance is encountered, the spin will flip
The gate electrodes allow the position of the phosphorus atom to be manipulated and control quantum entanglement of the adjacent phosphorous atoms.
Similar structures ( not shjown here) can be engineered as a “spin valve” utilizing the spin of an trapped electron to control current flow through a quantum dot by means of the Columnb blockade effect. Swithing the device on and off is accomplished in switching the spin polarization of the trapped electron.
Courtesy Eli Yablanovitch, UCLA

18. Challenges to Metrology
Instrumentation and techniques for
Identification and visualization of atomic species and structure
Observation of short-range and long-range order, defects
Device characterization

19. Summary
We have identified two major challenges for nanoelectronics, worthy of significant Government funding via NNI
We presented these findings to PCAST as part of their NNI review, and strategy development