1. ECE 551: Digital System Design & Synthesis
Lecture Set 7
7.1: Coding for if and case
(In separate file)
7.2: Coding logic building blocks
7.3: High-Performance Coding
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2. Overview Premise Basic coding for if and case Synopsis case directives
ECE Digital System Design & Synthesis Lecture 7.2 Coding for Synthesis of Combinational Logic - Coding Logic Building Blocks
Overview
Premise
Basic coding for if and case
Synopsis case directives
Late signal arrival coding for if and case
Data, Control
Coding Logic Building Blocks
Decoder, Priority Encoder, Reduction XOR, Multiplexer
High-Performance Methods
Datapath Duplication, Operator in if condition
General Coding Issues
Resource Sharing
Arithmetic Expression Optimization
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3. Decoder Decoder using indexing Decoder using for loop Comparison
Example 3-1 GHCS
Decoder using for loop
Example 3-3 GHCS
Comparison
Table Timing
Table Area
Table Compile Time
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4. Decoder Using Indexing in Verilog
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5. Decoder Using Loop in Verilog
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6. Decoder Verilog: Timing Comparison
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7. Decoder Verilog: Area Comparison
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8. Decoder Verilog: Compile Time Comparison
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9. Priority Encoder
Priority encoder using for loop starting at lowest priority bit
Example 3-5 GHCS
Figure Chain structure
Priority encoder using tree structure
Verilog not shown
Figure Tree structure
Comparison
Table Timing
Table Area
Table Compile Time
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10. Priority Encoder Verilog Loop - 1
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11. Priority Encoder Verilog Loop - 2
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12. Priority Encoder Loop Circuit
Very long delay due to cascades
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13. Priority Encoder Tree Verilog
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14. Priority Encoder Tree Circuit
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15. Reduction XOR Reduction XOR chain Reduction XOR tree Note
Example 3-8 GHCS
Figure 3-7 GHCS
Reduction XOR tree
Example 3-10 GHCS
Figure 3-8 GHCS
Note
Design Compiler can convert chain description to tree implementation if no intermediate points accessed in the chain. Thus, best to use tree structure.
OR chains with intermediate points become tree implementations.
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16. Reduction XOR Verilog Loop
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17. Reduction XOR Verilog Loop
Delay long due to cascade
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18. Reduction XOR Verilog Tree - 1
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19. Reduction XOR Verilog Tree - 2
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20. Reduction XOR Verilog Tree - 3
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21. Reduction XOR Circuit Tree
Delay reduced by 40 % (from 5 to 3 XOR levels)
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22. Multiplexer Multiplexer chain Multiplexer tree Comparison
Example 3-12 GHCS
Figure 3-9 GHCS
Multiplexer tree
Example 3-14 GHCS
Figure 3-10 GHCS
Comparison
Table Timing
Table Area
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23. Multiplexer Chain Verilog
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24. Multiplexer Chain Circuit
Long delay results from the cascade
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25. Multiplexer Tree Verilog - 1
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26. Multiplexer Tree Verilog - 2
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27. Multiplexer Tree Verilog - 3
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28. Multiplexer Tree Verilog - 4
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29. Multiplexer Tree Circuit
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30. Multiplexer Synth Comparison - 1
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31. Multiplexer Synth Comparison - 1
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32. Area, timing, and compile time are coding dependent
Summary
Area, timing, and compile time are coding dependent
Indexing and loops give different results
If delay is an issue, target tree rather than cascade circuits
Tree may also improve area
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