1. Case Study
Memory Controller
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2. Case Study (Memory Controller)
Case Study (Memory Controller)
BUS_ID
Address
Data
Reset OE
READY WE
FSM
SRAM
Memory
Array
BURST
ADDR1
READ_WRITE
ADDR0
CLK
دستگاههاي روي باس با اعلان bus idي mem_buffer (F3) دسترسي به باس را آغاز مي كنند.
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3. Case Study (Memory Controller)
Case Study (Memory Controller)
BUS_ID
Address
Data
Reset OE
READY WE
FSM
SRAM
Memory
Array
BURST
ADDR1
READ_WRITE
ADDR0
CLK
يك سيكل بعد, READ_WRITE = ‘1’ مي شود تا بگويد كه يك خواندن مي خواهد انجام شود (يا ‘0’ براي نوشتن).
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4. Case Study (Memory Controller)
Case Study (Memory Controller)
BUS_ID
Address
Data
Reset OE
READY WE
FSM
SRAM
Memory
Array
BURST
ADDR1
READ_WRITE
ADDR0
CLK
براي خواندن ممكن است 4كلمه اي (burst read)باشد: بايد در مدت اولين سيكل, burst فعال باشد.
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5. Case Study (Memory Controller)
Case Study (Memory Controller)
BUS_ID
Address
Data
Reset OE
READY WE
FSM
SRAM
Memory
Array
BURST
ADDR1
READ_WRITE
ADDR0
CLK
كنترلر به 4 محل از بافر دسترسي مي يابد (به محلهاي بعدي بعد از فعال كردنهاي متوالي ready دسترسي مي يابد).
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6. Case Study (Memory Controller)
Case Study (Memory Controller)
BUS_ID
Address
Data
Reset OE
READY WE
FSM
SRAM
Memory
Array
BURST
ADDR1
READ_WRITE
ADDR0
CLK
كنترلر oe را براي mem_buffer در طول خواندن فعال مي كند و دو بيت پايين آدرس را در حالت burst افزايش مي دهد.
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7. Case Study (Memory Controller)
Case Study (Memory Controller)
BUS_ID
Address
Data
Reset OE
READY WE
FSM
SRAM
Memory
Array
BURST
ADDR1
READ_WRITE
ADDR0
CLK
نوشتن هميشه يك كلمه اي است.
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8. Case Study (Memory Controller)
Case Study (Memory Controller)
BUS_ID
Address
Data
Reset OE
READY WE
FSM
SRAM
Memory
Array
BURST
ADDR1
READ_WRITE
ADDR0
CLK
هنگام نوشتن we فعال مي شود و data در محلaddress نوشته مي شود.
خواندن و نوشتن با اعلان ready خاتمه مي يابد.
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9. دياگرام حالت synch reset idle ready ready . burst ready ready Decision
Read_write
Read_write
ready
ready
. burst
ready
Write
read1
read2
read3
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10. Memory Controller براي همة حالتها مفروض است: ready state
Memory Controller
براي همة حالتها مفروض است:
ready
state
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11. VHDL Code (2-process) library ieee; use ieee.std_logic_1164.all;
entity memory_controller is port (
reset, read_write, ready,
burst, clk : in std_logic;
bus_id : in std_logic_vector(7 downto 0);
oe, we : out std_logic;
addr : out std_logic_vector(1 downto 0));
end memory_controller;
architecture state_machine of memory_controller is
type StateType is (idle, decision, read1, read2, read3, read4, write);
signal present_state, next_state : StateType;
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12. VHDL Code
begin
state_comb:process(reset, bus_id, present_state, burst, read_write, ready) begin
if (reset = '1') then
oe <= '-'; we <= '-'; addr <= "--";
next_state <= idle;
else
case present_state is
when idle => oe <= '0'; we <= '0'; addr <= "00";
if (bus_id = " “ and ready = ‘1’) then
next_state <= decision;
end if;
when decision=> oe <= '0'; we <= '0'; addr <= "00";
if (read_write = '1') then
next_state <= read1;
else read_write='0'
next_state <= write;
Don’t cares assigned to outputs  optimized
In every case, a signal must be assigned to the outputs; otherwise, unwanted latches.
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13. when read1 => oe <= '1'; we <= '0'; addr <= "00";
if (ready = '0') then
next_state <= read1;
elsif (burst = '0') then
next_state <= idle;
else
next_state <= read2;
end if;
when read2 => oe <= '1'; we <= '0'; addr <= "01";
if (ready = '1') then
next_state <= read3;
when read3 => oe <= '1'; we <= '0'; addr <= "10";
next_state <= read4;
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14. VHDL Code
when read4 => oe <= '1'; we <= '0'; addr <= "11";
if (ready = '1') then
next_state <= idle;
else
next_state <= read4;
end if;
when write => oe <= '0'; we <= '1'; addr <= "00";
next_state <= write;
end case;
end process state_comb;
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15. VHDL Code state_clocked:process(clk) begin if rising_edge(clk) then
present_state <= next_state;
end if;
end process state_clocked;
end;
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16. توليد خروجيها در ماشينهاي Moore
توليد خروجيها در ماشينهاي Moore
خروجيهايي كه از بيتهاي حالت به طور تركيبي ديكد شده اند: (كد قبل)
Inputs
Current-State
Next-State
State Registers
Next-State Logic
Output Logic
outputs
اشكال:
كند
مزايا:
گويايي كد
نگهداري آسانتر
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17. توليد خروجيها در ماشينهاي Moore
توليد خروجيها در ماشينهاي Moore
2) خروجيهايي كه از رجيسترهاي خروجي به طور موازي ديكد مي شوند:
Output Logic
outputs
Output Registers
Inputs
Current-State
Next-State
State Registers
Next-State Logic
انتساب به خروجيها مي تواند در خارج ازپروسسي كه انتقال حالات در آن تعريف مي شود انجام گيرد.
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18. architecture state_machine of memory_controller is
architecture state_machine of memory_controller is
type StateType is (idle, decision, read1, read2, read3, read4, write);
signal present_state, next_state : StateType;
signal addr_d: std_logic_vector(1 downto 0); D-input to addr f-flops
begin
state_comb:process(bus_id, present_state, burst, read_write, ready) begin
case present_state is
when idle => oe <= '0'; we <= '0'; addr is absent.
if (bus_id = " “ and ready = ‘1’) then
next_state <= decision;
else
next_state <= idle;
end if;
when decision=> oe <= '0'; we <= '0';
if (read_write = '1') then
next_state <= read1;
else read_write='0'
next_state <= write;
فرض: فقط براي addr اين كار را انجام مي دهيم (براي we و oe مشكل زماني نداريم)
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19. when read1 => oe <= '1'; we <= '0'; if (ready = '0') then
when read1 => oe <= '1'; we <= '0';
if (ready = '0') then
next_state <= read1;
elsif (burst = '0') then
next_state <= idle;
else
next_state <= read2;
end if;
when read2 => oe <= '1'; we <= '0';
if (ready = '1') then
next_state <= read3;
when read3 => oe <= '1'; we <= '0';
next_state <= read4;
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20. when read4 => oe <= '1'; we <= '0'; if (ready = '1') then
next_state <= idle;
else
next_state <= read4;
end if;
when write => oe <= '0'; we <= '1';
next_state <= write;
end case;
end process state_comb;
with next_state select D-input to addr flip-flops
addr_d <= "01" when read2, defined here.
"10" when read3,
"11" when read4,
"00" when others;
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21. state_clocked:process(clk, reset) begin if reset = '1' then
state_clocked:process(clk, reset) begin
if reset = '1' then
present_state <= idle;
addr <= "00"; asynchronous reset for addr flops
elsif rising_edge(clk) then
present_state <= next_state;
addr <= addr_d; value of addr_d stored in addr
end if;
end process state_clocked;
end state_machine;
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22. توليد خروجيها در ماشينهاي Moore
مشكلات:
2 FF اضافه.
براي انتشار بيتهاي حالت به FFهاي addr, از دو مدار تركيبي رد مي شود (اگر در PLD از 2 سلول استفاده كند مي تواند فركانس ماكزيمم را محدود كند)
Next-State Logic
State Registers
Output Logic
Inputs
Next-State
Current-State
outputs
Output Registers
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23. توليد خروجيها در ماشينهاي Moore
توليد خروجيها در ماشينهاي Moore
3) خروجيهايي كه مستقيماً در بيتهاي حالت انكد شده اند (Medvedev)
(مانند شمارنده ها):
outputs
Inputs
Next-State
State Registers
Current-State
Next-State Logic
State encoding بايد به دقت انجام شود.
ممکن است FFهاي بيشتري لازم داشته باشد.
براي خروجي به مدار ترکيبي نياز ندارد (سرعت بيشتر).
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24. State Encoding s2 s1 Addr(0) Addr(1) Idle decision Read1 1 Read2 Read3
فرض: فقط براي addr اين كار را انجام مي دهيم (براي we و oe مشكل زماني نداريم)
Addr(0)
Addr(1)
Idle
decision
Read1 1
Read2
Read3
Read4
Write s2 s1 1 x
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25. State Encoding we oe Addr(0) Addr(1) Idle decision Read1 1 Read2 Read3
اگر براي we و oe هم بخواهيم به همين صورت encode کنيم:
Addr(0)
Addr(1)
Idle
decision
Read1 1
Read2
Read3
Read4
Write we oe 1 s0 1
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26. VHDL Code architecture state_machine of memory_controller is
-- state signal is a std_logic_vector rather than an enumeration type
signal state : std_logic_vector(4 downto 0);
constant idle : std_logic_vector(4 downto 0) := "00000";
constant decision: std_logic_vector(4 downto 0) := "00001";
constant read1 : std_logic_vector(4 downto 0) := "00100";
constant read2 : std_logic_vector(4 downto 0) := "01100";
constant read3 : std_logic_vector(4 downto 0) := "10100";
constant read4 : std_logic_vector(4 downto 0) := "11100";
constant write : std_logic_vector(4 downto 0) := "00010";
begin
state_tr:process(reset, clk)
begin One-process FSM
if reset = '1' then
state <= idle;
elsif rising_edge(clk) then
case state is outputs not defined here
when idle =>
if (bus_id = " ") then
state <= decision;
end if; no else; implicit memory
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27. VHDL Code when decision=> if (read_write = '1') then
state <= read1;
else read_write='0'
state <= write;
end if;
when read1 =>
if (ready = '0') then
elsif (burst = '0') then
state <= idle;
else
state <= read2;
when read2 =>
if (ready = '1') then
state <= read3;
end if; no else; implicit memory
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28. end if; -- no else; implicit memory when read4 => state <= idle;
if (ready = '1') then
state <= read4;
end if; no else; implicit memory
when read4 =>
state <= idle;
when write =>
when others =>
state <= "-----"; don't care if undefined state
end case;
end if;
end process state_tr;
-- outputs associated with register values
we <= state(1);
oe <= state(2);
addr <= state(4 downto 3);
end state_machine;
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29. One-Hot Encoding Nتا FF براي N حالت. مثال: يک FSM با 18 حالت.
Sequential
State
00000
State0
00001
State1
00010
State2
00011
State3
00100
State4
00101
State5
00110
State6
00111
State7
01000
State8
01001
State9
01010
State10
01011
State11
01100
State12
01101
State13
01110
State14
01111
State15
10000
State16
10001
State17
Nتا FF براي N حالت.
مثال: يک FSM با 18 حالت.
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30. One-Hot Encoding فرض: بخشي از FSM: State15 State17 State2 cond3 cond1
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31. One-Hot Encoding الف) Sequential Encoding s4s3s2s1s0(بعدي)
State15
State17
State2
cond3
cond1
cond2
الف) Sequential Encoding
s4s3s2s1s0(بعدي)
cond1cond2cond3….
s4s3s2s1s0(جاري)
state0
state1
01111
00010
state2
...
state15
state16
10001
state17
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32. One-Hot Encoding الف) Sequential Encoding
s4s3s2s1s0(بعدي)
cond1cond2cond3….
s4s3s2s1s0(جاري)
state0
state1
01111
00010
state2
...
state15
state16
10001
State17
الف) Sequential Encoding
 مدار ترکيبي بسيار بسيار پيچيده.
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33. One-Hot Encoding مدار ترکيبي بسيار ساده اما تعداد FFها زياد
State
State0
State1
State2
State3
State4
State5
State6
State7
State8
State9
State10
State11
State12
State13
State14
State15
State16
State17
مدار ترکيبي بسيار ساده
اما تعداد FFها زياد
18 معادلة بسيار ساده به جاي 5 معادلة بسيار پيچيده
 سطوح کمتر مدار بين رجيسترهاي حالت
 فرکانس بالاتر
مناسب براي FPGA.
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34. Power Reduction
State assignment مناسب مي تواند توان مصرفي را کاهش دهد.
مثلاً One-hot در هر سيکل، فقط 2 تغيير سيگنال لازم دارد.
عوامل ديگر:
تعداد زيادي رجيستر مي خواهد
مدار منطقي توليد حالت بعدي
 بايد آزمايش کرد.
Gray Encoding: براي FSMهاي شبيه شمارنده ها (بدون شاخه) مناسب تر.
attribute fsm_encoding: string;
attribute fsm_encoding of
{entity_name|signal_name }: {entity|signal} is
"{auto|one-hot|sequential|gray|johnson|speed1|user}";
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35. Pipelining
ايدة اصلي: عمليات datapath بزرگي را که در يک سيکل ساعت انجام مي شود به چند عمل کوچک که در چند سيکل انجام مي شوند تقسيم کنيم:
Datapath Operation
Inputs
outputs
Registers
tp= x
Part 1
Inputs
outputs
Registers
tp= x/3
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36. Pipelining
f تقريباً 3 برابر مي شود (صرف نظر از زمانهاي tco و tsu براي رجيسترهاي (pipeline
throughput 3 برابر مي شود اما خروجيها 3 کلاک ديرتر حاضر مي شوند: latency
و نيز هزينة افزودن رجيسترها را دارد.
بيشتر FPGAها مشکلي ندارند اما در CPLDها pipeline کمتر به کار مي رود.
CPLDها در يک pass از logic array، عمليات زيادي را مي توانند انجام دهند
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37. A Systolic FFT Architecture for Real Time FPGA Systems
ANIMATION EXAMPLE, taken from:
A Systolic FFT Architecture for Real Time FPGA Systems
Preston Jackson, Cy Chan, Charles Rader, Jonathan Scalera, and Michael Vai
HPEC 2004
29 September 2004
This work was sponsored by DARPA ATO under Air Force Contract F C Opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the Department of Defense. 1 1

38. Example: Baseline Parallel Architecture1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10 11 11 11 11
This is the parallel FFT architecture. When compared with a direct implementation of the DFT, it removes redundant calculations. 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 15 16 16 16 16
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39. Parallel-Pipelined Architecture1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10 11 11 11 11
The parallel implementation is easily pipelined. This architecture would be 100% efficient if it could be supplied with enough data. However, the number of input pins needed to keep an 8192-point FFT would be 65606, with only 8-bit inputs. Also, A/D converters cannot keep up with this rate of data generation. Thus, a serial design is often used to match with the serial input. 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 15 16 16 16 16
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40. src_op
Example: AMD AM2901
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41. AMD AM2901 library ieee; use ieee.std_logic_1164.all;
use work.numeric_std.all;
use work.am2901_comps.all;
entity am2901 is port(
clk, rst: in std_logic;
a, b: in unsigned(3 downto 0); address inputs
d: in unsigned(3 downto 0); direct data
i: in std_logic_vector(8 downto 0); micro instruction
c_n: in std_logic; carry in
oe: in std_logic; output enable
ram0, ram3: inout std_logic; shift lines to ram
qs0, qs3: inout std_logic; shift lines to q
y: buffer unsigned(3 downto 0); data outputs (3-state)
g_bar,p_bar:buffer std_logic; carry generate, propagate
ovr: buffer std_logic; overflow
c_n4: buffer std_logic; carry out
f_0: buffer std_logic; f = 0
f3: buffer std_logic); f(3) w/o 3-state
end am2901;
مرتضي صاحب الزماني

42. مرتضي صاحب الزماني architecture am2901 of am2901 is
alias dest_ctl: std_logic_vector(2 downto 0) is i(8 downto 6);
alias alu_ctl: std_logic_vector(2 downto 0) is i(5 downto 3);
alias src_ctl: std_logic_vector(2 downto 0) is i(2 downto 0);
signal ad, bd: unsigned(3 downto 0);
signal q: unsigned(3 downto 0);
signal r, s: unsigned(3 downto 0);
signal alu_out: unsigned(3 downto 0);
begin
-- instantiate and connect components
u1: ram_regs port map(clk => clk, rst => rst, a => a, b => b, alu_out => alu_out,
dest_ctl => dest_ctl, ram0 => ram0, ram3 => ram3,
ad => ad, bd => bd);
u2: q_reg port map(clk => clk, rst => rst, alu_out => alu_out, dest_ctl => dest_ctl,
qs0 => qs0, qs3 => qs3, q => q);
u3: src_op port map(d => d, ad => ad, bd => bd, q => q,
src_ctl => src_ctl, r => r, s => s);
u4: alu port map(r => r, s => s, c_n => c_n, alu_ctl => alu_ctl,
alu_out => alu_out, g_bar => g_bar, p_bar => p_bar,
c_n4 => c_n4, ovr => ovr);
u5: out_mux port map(ad => ad, alu_out => alu_out, dest_ctl => dest_ctl,
oe => oe, y => y);
-- define f_0 and f3 outputs
f_0 <= '0' when alu_out = "0000" else 'Z';
f3 <= alu_out(3);
end am2901;
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43. src_op
Pipelined AM2901
براي هماهنگي زماني خروجيها
مرتضي صاحب الزماني

44. Pipelined AMD AM2901 library ieee; use ieee.std_logic_1164.all;
use work.numeric_std.all;
use work.am2901_comps.all;
entity am2901 is port(
clk, rst: in std_logic;
a, b: in unsigned(3 downto 0); address inputs
d: in unsigned(3 downto 0); direct data
i: in std_logic_vector(8 downto 0); micro instruction
c_n: in std_logic; carry in
oe: in std_logic; output enable
ram0, ram3: inout std_logic; shift lines to ram
qs0, qs3: inout std_logic; shift lines to q
y: buffer unsigned(3 downto 0); data outputs (3-state)
g_bar_q,p_bar_q:buffer std_logic; carry generate, propagate
ovr_q: buffer std_logic; overflow
c_n4_q: buffer std_logic; carry out
f_0: buffer std_logic; alu_out = 0
f3: buffer std_logic); alu_out(3) w/o 3-state
end am2901;
مرتضي صاحب الزماني

45. مرتضي صاحب الزماني architecture am2901 of am2901 is
alias dest_ctl: std_logic_vector(2 downto 0) is i(8 downto 6);
alias alu_ctl: std_logic_vector(2 downto 0) is i(5 downto 3);
alias src_ctl: std_logic_vector(2 downto 0) is i(2 downto 0);
signal ad, bd: unsigned(3 downto 0);
signal q: unsigned(3 downto 0);
signal r, s: unsigned(3 downto 0);
signal alu_out, alu_out_q: unsigned(3 downto 0);
begin
-- instantiate and connect components
u1: ram_regs port map(clk => clk, rst => rst, a => a, b => b, alu_out => alu_out_q,
dest_ctl => dest_ctl, ram0 => ram0, ram3 => ram3,
ad => ad, bd => bd);
u2: q_reg port map(clk => clk, rst => rst, alu_out => alu_out _q, dest_ctl => dest_ctl,
qs0 => qs0, qs3 => qs3, q => q);
u3: src_op port map(d => d, ad => ad, bd => bd, q => q,
src_ctl => src_ctl, r => r, s => s);
u4: alu port map(r => r, s => s, c_n => c_n, alu_ctl => alu_ctl,
alu_out => alu_out, g_bar => g_bar, p_bar => p_bar,
c_n4 => c_n4, ovr => ovr);
u5: out_mux port map(ad => ad, alu_out => alu_out _q, dest_ctl => dest_ctl,
oe => oe, y => y);
-- define f_0 and f3 outputs
f_0 <= '0' when alu_out _q = "0000" else 'Z';
f3 <= alu_out _q(3);
No change
مرتضي صاحب الزماني

46. Pipelined AMD AM2901 مرتضي صاحب الزماني process (clk)
if (rising_edge(clk) then
alu_out_q <= alu_out;
g_bar_q <= g_bar;
p_bar_q <= p_bar;
ovr_q <= ovr;
c_n4_q <= c_n4;
end if;
end process;
end am2901;
مرتضي صاحب الزماني