LOW VOLTAGE OP AMPS We will cover: Methodology:

LOW VOLTAGE OP AMPS We will cover: Methodology:
Low voltage input stages Low voltage bias circuits Low voltage op amps Examples Methodology: Modify standard circuit blocks for reduced power supply voltage Explore new circuits suitable for low voltage design

Analog design challenges
Analog circuits suffer from nonlinear mechanisms while mitigating to newer CMOS technology Poorer transistor properties Worse gate leakage Figure 1 Voltage gain of transistors as a function of the gate-overdrive voltage with VDS proportional to nominal supply voltage and L=1µm for four technologies Figure 2 Output IP3 of transistors as a function of the gate-overdrive voltage with VDS proportional to nominal supply voltage and L=1µm for four technologies Figure 3 Low-frequency current gain of MOS transistors as a function of gate length (L) in 65nm and 90nm CMOS technologies at VGS = 0.5V A.-J. Annema, B. Nauta, R. van Langevelde, and H. Tuinhout, “Analog circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits, vol 40, pp. 132−143, Jan

ITRS Projection – near term

ITRS Projection – longer term

Low-Voltage, Strong-Inversion Operation
Reduced power supply means decreased dynamic range Nonlinearity will increase because the transistor is working close to VDS(sat) Large values of λ because the transistor is working close to VDS(sat) Increased drain-bulk and source-bulk capacitances because they are less reverse biased. Large values of currents and W/L ratios to get high transconductance Small values of currents and large values of W/L will give smallVDS(sat) Severely reduced input common mode range Switches will require charge pumps

Input common mode range drop
VDD – VDS3sat + VT1 > vicm > VDS5sat + VT1 + Von1 > vicm > , unsymmetric!

p-n complementary input pairs
n-channel: vicm > VDSN5sat + VTN1 + VonN1 p-channel: vicm <VDD- VDSP5sat - VTP1 - VonP1

Non-constant input gm N

constant input gm solution
Let Vb1 depends on Vicm so that Mb1 is turned on when MN1,2 are turned off, and Ip becomes 4 times. Similarly when MP1,2 are off, In becomes 4 times. When both pair on, In and Ip are bothe 1 times

Set VB1 = Vonn and VB2 = Vonp

Rail-to-rail constant gm input
When both on, I5=I1=I12=IBP=Ip; I11=I7=I6=IBN=In As Vin+ and Vin- reduce, MN1,2 begins to turn off, MNC1,2 also begins to turn off. I7 reduces, so does I8. I9 = I12-I8 increases, so does I10, which is 3(I12-I8)=3(Ip-In), which becomes 3Ip when n-pair turns off.

Complementary input stage with rail-to-rail Vicmr and constant gm
aIp Ip aIn 3(Ip-In) aIn a(Ip-In) BP Vbp in+ in- NC1,2 PC1,2 N1 P1 P2 N2 Vi+ Vi- Vi+ Vi- Vi- Vi+ ip+ ip- BN Vbn 3(In-Ip) aIp aIn In aIp a:3 1 2 3 4 a(In-Ip)

Folded cascode stage: summing current and convert to voltage
Vxx in+ =+gmn1*vid/2 in- = -gmn1*vid/2 ip+ =+gmp1*vid/2 ip- = -gmp1*vid/2 io1- =ip- - in+ = -(gmp1+gmn1)*vid/2 io1+=ip+ - in- = (gmp1+gmn1)*vid/2 Vo1- = io1- /go1 Vo1+ = io1+ /go1 Vo1d = (Vo1+ -Vo1+ ) = vid *(gmp1+gmn1)/go1 in+ in- Vyy -in+ Vo1+ Vo1- io1-=ip- - in+ Vbb -ip- ip+ ip- Vzz

Folded cascode stage: feedback to reduce go1
gds4 Vxx M4 M4 vcp gds3 gm3vcp Vyy M3 M3 gmn1vd/2 gdsn1 i vo1+ Vbb gm2bvcn +gm2bvcp +gmb2bvcn gm2avcn +gmb2avcn M2b M2a M2a M2b gds2b gds2a vcn M1 M1 Vzz gds1 Show that it is possible to make gain (vo1/vd) infinity by proper sizing.

Folded cascode stage: feedback to reduce go1, alternative
gds4 Vxx M4 M4 vcp gds3 gm3vcp Vyy M3 M3 gmn1vd/2 gdsn1 i vo1+ Vbb gm2vcn +gmb2vcn M2 M2 gds2 vcn gds1b gm1bvcp M1a Vzz gds1 M1b M1a M1b

In either case, you can set vd=0, write KCL’s for the vn, vn and vo1 nodes, eliminate vn and vp, obtain expression in vo1 alone, set coefficient to zero, this gives conditions for go=0. From that, you can solve for gm for the feedback transistor and see how that can be realized. For example, in the first choice, if you make gds of M1 and M3 4 times as large as the other transistors, it becomes relatively simpler to meet the conditions. Small signal analysis for 2nd choice is easier, but quiescent voltage a concern. You can also feedback to PMOS transistors. Feeding back to top or bottom transistors faces big challenges when supply voltage increases. If the whole M2 (or M3 in the P version) is controlled by feedback, then the VgsQ of M2 is independent of supply.

Regulated Cascode for gain improvement
VD Vxx VG M4 M4 k VG3 - - M3 M3 VS A3 + + A4 VG2 + - + - M2 M2 A1 A2 VD VG M1 M1 Vzz VS If you regulate, you have to regulate all four.

Second stage M4 Vxx M4 M7 M7 Vyy M3 M3 Vbb M2 M2 M6 M6 M1 Vzz M1

Second stage push pull: Monticelli style
Vxx M4 M7 M7 Vyy M3 M3 Vbp Vbn Vbb M2 M2 M6 M6 M1 Vzz M1 Requires: VDD-VSS > Vgs6+Vgs7+Vdssat_floating_CS D. M. Monticelli, “A quad CMOS single-supply Op Amp with rail-to-rail output swing,” IEEE J.Solid-State Circuits, no. 6, pp. 1026–34, Dec

Unpredictable current in second stage
Don’t do M4 Vxx M4 M7 M7 Vyy M3 M3 Vbb M2 M2 M6 M6 M1 Vzz M1 Unpredictable current in second stage

These circuits can come from the same biasing circuit for the main amplifier.
So, no extra current, power consumption, noise, and offset introduced. Vxx Vbn Vbp Vzz So, Vg6Q = Vzz This sets Id6.Q So, Vg7Q = Vxx This sets Id7Q.

Floating CS do not change ro1 or DC gain
gds4 The impedance looking down from Vo1+ is Rn To find impedance looking up from Vo1+, inject a test current i up. V’o1+ = i*Rp i_gdsn/p = (i-gmnvo1++gmpv’o1+) Vo1+=V’o1+ + i_gdsn/p /(gdsn + gdsp) Vo1+=i*Rp+(i-gmnvo1++gmpi*Rp) /(gdsn+gdsp) Vo1+(1+gmn /(gdsn+gdsp)) =i*{Rp[1+gmp/(gdsn+gdsp)] +1/(gdsn+gdsp)} Vo1+/I =Rp gmp/gmn Rp gds3 gm3vcp V’o1+ gmnvo1+ gdsn gdsp -gmpv’o1+ vo1+ gm2avcn +gmb2avcn gds2a Rn gds1 So, size them so that gmp ≈ gmn Note: gmn and gmp include possible body effects.

To the two gate terminals of M6 and M7, the two floating CS appears as a voltage source providing a voltage offset between the gates. The impedance seen by the two gate terminals can be calculated by: Rs = (Vgp – Vgn)/(current through the floating CS) = (Vgp – Vgn)/(gmp*Vgp – gmn*Vgn + (Vgp – Vgn)*(gdsn+gdsp)) ≈ 1/(gmp + gdsn+gdsp) ≈ 1/gmp The above assumed that the NMOS and PMOS are sized to have the same gm. Also, the calculation is only valid when both NMOS and PMOS are fully on and both in saturation. When Vo is experiencing large swings, these conditions are not met. And the voltage difference between the two gate terminals no longer remain constant.

Differential signal path compensation
Vxx M4 M7 M7 Vyy M3 M3 Vbb M2 M2 M6 M6 M1 Vzz M1

In order for M6 and M7 to have well defined quiescent current, we have to bias the circuit so that at Q, Vd2 = Vzz. This is naturally provided by the usual bias generator: Problem: Vd2 is a high impedance node, small current mismatch in M1 and M4 leads to significant voltage change at vd2, which in turn changes the biasing current in the output stage. Solution: use feedback to stabilize common mode of Vd2. Vbb Vzz

Vzz Vd2L Vd2R Feedback to M4 or part of it Since Vd2L and Vd2R are normally nearly constant. We do not need to worry about the input range accommodation for this circuit. Size the circuit so that, when vid =0, Id6 remain near desired level over all process variations in M1 and M4.

Current sensors Quiescent biasing
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998 Quiescent biasing Current sensors

Vo+ and Vo- also need common mode stabilization
M7t’s are in triode M7t M7t M7 M7 Vocmd R R C C M6 M6 Choose R to a couple times bigger than Ro Choose C to be near or a couple times larger than Cgs of CMFB circuit.

M7t’s are in triode Insert these M7t M7t M7 M7 Vocmd R R C C M6 M6

Why RC in common mode detector
KCL at V: (V1 – V)/R + (V2 – V)/R = V * sCgs (V1 + V2)/R = V(sCgs + 2/R) V = (V1 + V2)/2 * 1/(1 + sRCgs/2) When |s| =|jw| << 2/RCgs, V ≈ (V1 + V2)/2 Otherwise V is not close to common mode To have CM detector work up to GB, R << 2/(2pGB*Cgs) V1 R V Cgs R V2

KCL at V: (V1 – V)(1/R +sC) + (V2 – V) (1/R +sC) = V * sCgs (V1 + V2) (1/R +sC) = V(sCgs + 2/R +2sC) V = (V1 + V2)/2 * (1 + sRC)/(1 + sRC + sRCgs/2) As long as Cgs/2 < C, at all freq: V ≈ (V1 + V2)/2 V1 R C V Cgs C R V2 Hence, the RC network acts as a better CM detector

Why CMBF to M7t instead of first stage:
For CM behavior, assume DM=0. Vo1+=Vo1-, and Vo+=Vo-=Vocm. Without CMFB effect, at Q, Vo+ will be equal to Vg, which may be far below desired Vocm level. With CMFB connected, the feedback effect will drive Vo1 so as to move Vo+ up to the desired Vocm level. Since Vo1+ and Vo1- have a competing action on Vo+, it may take quite bit Vo1 movement to achieve the desired Vo+ movement, causing the biasing current in the second stage to be much larger than what is intended. Vo1+ Vo1- Vo+ Vg

Compensation for diff signal path closed-loop stability
Vxx M4 M7 M7 Vyy M3 M3 CC CC Vbb M2 M2 M6 M6 M1 Vzz M1

At relatively low frequency:
Because of gain from Vo1 to Vo, small signal Vo1 is much smaller than small signal Vo. Small signal current in compensation network is approximately Vo/(1/gmz+1/sCc). This current is injected to the Vo1 node. Alternatively, a similar current can be injected: Impedance looking into a cascode node is about 1/gm Connecting Cc to a cascode node generates a current of the form Vo/(1/gm +1/sCc) Because the base transistor is a current source, this small signal current goes to the Vo1 node Even at high frequency, the current form is still valid.

Alternative compensation

In the Cc+Mz connection,
Bias voltage of Mz can be matched to track bias voltage of M6  robustness to process and temperature variations Size of Mz can be parameter scanned so as to place zero to cancel the secondary pole of the amplifier In the Cc to cascode connection, Bias voltage can still be derived using current mirrors from a single current source,  still have process and temperature tracking But size of cascode transistor is determined based on folded cascode stage design Cannot arbitrarily choose its size without considerations for output impedance at Vo1, gain of op amp, and so on.

Alternative compensation

Use open loop Vicm sweep to find a “sweet spot” for your Vicm
Vo+, Vo- Vicm Vicm

With Vicm at “sweet spot”, sweep Vin near Vicm with very fine steps (uV)
Vo+ Vo- Vicm Vin Vin d(Vo+-Vo-) dVin Vo+-Vo- Vin

Folded cascode stage: summing current and convert to voltage
3:1 Vb2 CC Vi- Vo+ VCMFB Vb1 Vo+ Vo- Vo-

Summing circuit to add n-signal and p-signal together

Rail-to-rail constant gm input
Coban and Allen, 1995

The composite transistor

Bulk-Driven MOSFET

Bulk-Driven, n-channel Differential Amplifier
I1=I2=I5/2 As Vic varies, Vd5 changes and gmb varies  Varied gain, slew rate, gain bandwidth; nonlinearity; and difficulty in compensation

Bulk-driven current mirrors
Increased vin range and vout range

Traditional techniques for wide input and output voltage swings
Iin+Ib Ib Ib Iin VT+2Von >2Von 1/4 1 + 1 VT+Von Von – Von VT+Von 1 1

Traditional techniques for wide input and output voltage swings
Iin Iin Ib Ib + VT+2Von Io Veb >2Von – 1/4 1 Von Von VT+Von 1 1

A 1-Volt, Two-Stage Op Amp
Uses a bulk-driven differential input pair, wide swing current mirror load, and emitter follower level shifter

Op Amp Performance

Frequency Response

Low voltage VBE and PTAT reference

Threshold Voltage Tuning for low power supply voltages operation

Implementation of the voltage sources

A low voltage Op Amp core

Op Amp Implementation Clock booster Bias voltage generator
Leakage from M3 make less than 2VDD, two stages are used. R is used for Clock booster Bias voltage generator

Clock booster (doubler)
CB1 >> CBL

Experimental Results Power supply 750mV Slew Rate 3.1V/uS GB 3.2MHz
DC gain 62dB Input offset voltage 2.2mV Input common mode range 0.1V-0.58V Output swing for linear operation 0.31V-0.58V PSRR at DC 82dB CMRR at DC 56dB Total power consumption 38.3uW Power supply range…… Offset voltage package

Common mode feedback for low voltage

1.5v op amp for 13bit 60 MHz ADC

Output Stage and CMFB

Folded cascode with AB output
Lotfi 2002

Simulated performance
0.25 um process 1.5 V power supply 82 dB DC gain 2 V p-p diff output swing 170 MHz 10 pF load 77o PM with b = 1/5 0.02% 1V step settling time: 8.5 ns Full output swing Op Amp power: 25 mW

Differential difference input AB output
Alzaher 2002

Nested Miller Cap Amplifier
Not much successes

Low voltage amp

LOW POWER OP AMPS Op Amp Power = (VDD-VSS)*Ibias
Reduce supply voltage: effect is small Many challenges in low voltage design same as before Reduce bias: factor of hundred reduction Weak inversion operation Nano-amp to small micro-amp currents Needs small current biasing circuits and small current reference generators Needs output stage to drive the load Design it so that it consume tiny quiescent power But generate sufficient current for large signals Tradeoff speed for reduced power

Sub-threshold Operation
Most micro-power op amps use transistors in the sub-threshold region. np~1.5; nn~2.5

Two-Stage, Miller Op Amp in Weak Inversion
At VDD-VSS=3V, ID5=0.2uA, ID7=0.5uA, got A=92dB, GB=50KHz, P=2.1uW

Push-Pull Output in Weak Inversion
First stage gain Total gain S=W/L

Increasing gain What is VON? L5=L12, W12=W5/2 S13<<S4 go
Gain=gm/go

Increasing Iout with positive feedback
When vi1>vi2 i2>i1 i26=i2-i1>0 i27=0 i28=A*i26 itail=I5+i28 =i1+i2 i2/i1=e(vi1-vi2)/nvt =evin/nvt i2=i1evin/nvt I5+ A*(evin/nvt-1)i1= (evin/nvt+1)i1 i1=I5 /{A+1-(A-1)evin/nvt)}

A=0 is normal case A > 0 can greatly enhance available output current for load driving

i1+i2 much faster than i2-i1
as vin  New i1+i2 i2=i1evin/nvt i1=i2 A=3 I5 i1+i2=I5 A=2 A=1 A=0 I5 i2

DC Offset (Self-mixing)
A D A w c D w c

Fully differential, with DC gain >= 90 dB, GB>=50MHz, CL=2p on each side, slew rate >= 100V/us, small signal step response (closed-loop with inverting |gain|>=1) overshoot <= 10% and 0.1% settling time <=75ns. (these are nearly the same as op amp 1) Now the goal is to minimize total quiescent current. The following becomes much tougher: Total quiescent current budget must be at least 10 times smaller. Output differential swing must be near rail to rail Input common mode range must cover rail to rail Vdd – Vss can change from 5 V all the way down to 2.2 V. Most of the specs should remain nearly constant over ICMR and over Vdd

Strategies for rail to rail ICMR
Complimentary input: Vbc + Veb1  Vdd – Vdsat5 + Vth1 Vss + Vdsat9 – Vth3  Vbbc – Veb3 Total range: Vss > Vss + Vdsat9 – Vth3  Vdd – Vdsat5 + Vth1 > Vdd Need: Vbc +Veb1 <= Vbbc – Veb3 for all Vdd

Dual n-channel input for PVT-R
Vss  Vbc + Veb1 Vbc + Veb1  Vdd – Vdsat5 + Vth1 Ifc Ii Vins+ and Vins- are shifted up by about Vbc + Veb1=Vthn+Veb13+Veb13c+Veb2

Here: Vins+ and Vins- are shifted up by Vthp+Veb5, which can be made to be about Vthn+Veb13+Veb13c+Veb2

Level Shifter Analysis
Transfer Function Pole Zero Model Since |p|<|z|, there is phase delay. Delay is max at sqrt(pz). To make delay small enough, need |p| >> UGF of Ab. So make gm large, and Cgs large relative to CL. What is RL? What about gmb effect?

When Vin+ and Vin- are high, MS3 and MS4 are fully on.
All the current in MS3&4 are mirrored to MS6. MS7 will have 0 current, so does MS8. That turns off the shift-input pair. As Vin+- drop, the right tail current source is pushed into triode. I_MS5 decreases, I_MS7 increases, and the shift-input pair is being turned on. The transition range depends on Veb of tail cascode and of input pair. When both pairs are partially on, there is no high impedance node.

Will this addition make the drain of MS6 always low impedance?
Current in this needs to be increased to accommodate the added current

Will this work?

But quiescent Io depends on Vo1Q, and uncontrolled.
Push-pull output Main goal: make Vo swing from Vss to Vdd. Equivalent to double the output stage gm, ↑gain, GB Make slew rate higher than Io/CL 1:M Io/M Io 1:M Make output Vebo small. When Vo1 swings, say by 2.1Vebo, ICL can be 10xIo! But quiescent Io depends on Vo1Q, and uncontrolled.

Output quiescent current control by local CMFB.
Vo1 CMFB 1:M Itail Io/M Io/M Io 1:M 1:1 match

M1a+M1b forms diff pair with M2
Vo1+/- swing is about +- 2.# * Vebo, or about to 0.4 V, so M1a and M1b should have Veb about equal to 2*Vebo. Vb3 should be selected so that M12 is still in saturation when Vo1 drops to a little below Vthn-Vebo. The Veb of M12, M10, and the size of diode connected CMFB1 transistor should be such that M 10 is guaranteed to be in saturation. Note that there is only one high impedance node (Vo1 node) in this CMFB loop, hence the loop UGF can be made high and still maintain good stability.

Vo+ and Vo- also need common mode stabilization
M17t and M21t are in triode M21t M17t M21 M17 M18 Vocmd M19 M15 R R C C M20 M16 Choose R to a couple times bigger than Ro Choose C to be near or a couple times larger than Cgs of CMFB circuit.

M:1 1:M Vxx Vxx M:1 1:M Vocmd R R C C

KCL at V: (V1 – V)/R + (V2 – V)/R = V * sCgs (V1 + V2)/R = V(sCgs + 2/R) V = (V1 + V2)/2 * 1/(1 + sRCgs/2) When |s| =|jw| << 2/RCgs, V ≈ (V1 + V2)/2 Otherwise V is not close to common mode To have CM detector work up to GB, R << 2/(2pGB*Cgs) V1 R V Cgs R V2

KCL at V: (V1 – V)(1/R +sC) + (V2 – V) (1/R +sC) = V * sCgs (V1 + V2) (1/R +sC) = V(sCgs + 2/R +2sC) V = (V1 + V2)/2 * (1 + sRC)/(1 + sRC + sRCgs/2) As long as Cgs/2 < C, at all freq: V ≈ (V1 + V2)/2 V1 R C V Cgs C R V2 Hence, the RC network acts as a better CM detector

Why CMBF to M17t instead of first stage:
For CM behavior, assume DM=0. Vo1+=Vo1-, and Vo+=Vo-=Vocm. Without CMFB effect, at Q, Vo+ will be equal to Vg, which may be far below desired Vocm level. With CMFB connected, the feedback effect will drive Vo1 so as to move Vo+ up to the desired Vocm level. Since Vo1+ and Vo1- have a competing action on Vo+, it may take quite bit Vo1 movement to achieve the desired Vo+ movement, causing the biasing current in the second stage to be much larger than what is intended. Vo1+ Vo1- Vo+ Vg

Current budgeting SR >= dVo/dt = 2*dVo+/dt
At slewing: dVo+/dt = I_CL / CL. Let Io_slew = SR * CL /2. So we need Iomax > Io_slew. If Iomax can be as high as Kpp x IoQ, the we have IoQ >= SR * CL /(2Kpp) Also, If the second stage have over drive voltage VEB2, Vo1 must be able to swing (rt(Kpp)-1)*VEB2 above and below Vo1Q. Vo1Q must be stabilized by common mode feedback, so that the desired quiescent current in the second stage is achieved.

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