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Short Retrospective on RISC

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Presentation on theme: "Short Retrospective on RISC"— Presentation transcript:

1 Short Retrospective on RISC

2 Open Microcode Compiler Generates Lowest Level of Interpretation
HLL ISA Microcode ISA Control Signals Compiler Generates Lowest Level of Interpretation No Microcode Single Cycle Execution Complex Compiler vs. Complex Hardware Issues: Bandwidth, Compiler Complexity, On Chip Tailoring Wasted Cycles

3 What is it? Originally : Open Microcode
John Cocke (1970’s) 1980: Simple Set of Simple Instructions Sequin, Patterson (1980) 1989: Short, Tight Pipelines John Hennessy 1994: VLIW Wall Street Journal

4 Characteristics Fixed Length, Uniform Decode Instructions No Microcode
Load/Store Larger Register Set Delayed Branch Register Windows

5 What is it (Non-Technical)
Everything Since 1983 “Good” Motorola Article Microcoded RISC Article MicroVAX – 2 VAX 9000 Literature SPARC System The “RISC” Core

6 Why Did It Happen Masterful Marketing Time-to-Market Curve
Published Berkeley Benchmarks RISC Chip in Weeks, VAX in Years Simple is Beatiful 4-on-floor vs. Automatic Time-to-Market Curve VAX 8600 Was Very Late Track Technology Curve Why Was it Taken Seriously HP Bet the Family Store

7 Comments on the Hype Simple is Beautiful Published Berkeley Benchmarks
Complex Instructions Provide Opportunity for Speed-Up 1st add Fl.Pt. Graphics MMX Compilers Never Use It Some BAD Implementations One Compiler or All Compilers Published Berkeley Benchmarks Why did H-P jump in ?

8 The Players The University Experiments Commercial Products
RISC (Berkeley, 1980, Patterson, Emphasis on “Simple”) MIPS (Stanford, 1981, Hennessy, Emphasis on Compiler) Commercial Products HP-PA (The IBM Team, Emphasis on Compiler) SPARC (Berkeley RISC) MIPS (Simple) AMD 29000 Motorola 88000 IBM RISC System 6000 (Return to Past) …

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