1. PACE: Power-Aware Computing Engines
Energy-Conscious Compilers
Energy-Exposed Architectures
New Ideas:
Microprocessor architectures that expose energy consumption to software
Energy-conscious compiler analyses that minimize switching activity in processors
Simulator technology for fast accurate processor energy-performance analysis
GOAL: Reward compile-time knowledge with run-time energy savings
Rethink Hardware-Software Interface for Power-Aware Computing
Schedule
Impact:
New integrated architecture and compiler techniques for power-aware systems
Improve processor energy-delay product by 5-100x for automatically compiled code
Fast ( kHz) and accurate (<10% error) energy-performance simulation techniques for low-power microprocessors
Architecture
Baseline
Single Tile
Multi-Tile
Energy-Performance Simulator
Baseline
Single Tile
Multi-Tile
Compiler
Baseline
Single Tile
Multi-Tile
Application Evaluation
Single Tile
Multi-Tile
Baseline
Jun’00
Sep’00
Dec’00
Mar’01
Jun’01
Sep’01
Dec’01
Mar’02
Jun’02
Sep’02
MIT Laboratory for Computer Science
Krste Asanovic, Saman Amarasinghe, Martin Rinard