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Overview of SHARC processor ADSP and ADSP-21065L

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Presentation on theme: "Overview of SHARC processor ADSP and ADSP-21065L"— Presentation transcript:

1 Overview of SHARC processor ADSP-21061 and ADSP-21065L
* 07/16/96 This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentation In Slide Show, click on the right mouse button Select “Meeting Minder” Select the “Action Items” tab Type in action items as they come up Click OK to dismiss this box This will automatically create an Action Item slide at the end of your presentation with your points entered. Overview of SHARC processor ADSP and ADSP-21065L M. R. Smith, Electrical and Computer Engineering, University of Calgary, Alberta, Canada ucalgary.ca *

2 To be tackled today Reference sources Register file and operations
Memory configuration and operations Sample instructions Program Flow Some warnings of expected errors Code review and code review standards Some recent architectural advances Tiger-SHARC and Hammerhead-SHARC 11/27/2018 ENCM Review of SHARC Processor Copyright

3 This is a FAMILIARIZATION lecture Learn a useful subset of instructions by OSMOSIS later on in course

4 Reference Sources ADSP-2106x SHARC User’s Manual 2nd edition, Analog Devices -- provided to everybody ENCM515 SHARC Reference card ENCM515 Course, Reference and Laboratory Notes SHARC Developers CD (Borrow from office and install the manuals) SHARC Navigator Tutorial Tool 11/27/2018 ENCM Review of SHARC Processor Copyright

5 Picture Source SHARC Navigator Tutorial Tool T. Talik Alukaidey Dept. of EEE Uninversity of Hertfordshire, Hatfield, U.K. 11/27/2018 ENCM Review of SHARC Processor Copyright

6 ADSP-2106x Core Architecture
* ADSP-2106x Core Architecture 07/16/96 DAG 2 8 x 4 x 24 DAG 1 8 x 4 x 32 CACHE MEMORY 32 x 48 PROGRAM SEQUENCER PMD BUS DMD BUS 24 PMA BUS PMD DMD PMA 32 DMA BUS DMA 48 40 JTAG TEST & EMULATION FLAGS FLOATING & FIXED-POINT MULTIPLIER, FIXED-POINT ACCUMULATOR 32-BIT BARREL SHIFTER FLOATING-POINT & FIXED-POINT ALU REGISTER FILE 16 x 40 BUS CONNECT TIMER *

7 Register File and A.L.Us Key issues 5 data paths FROM ALU
5 data paths TO ALU Highly parallel operations UNDER THE RIGHT CONDITIONS 11/27/2018 ENCM Review of SHARC Processor Copyright

8 Register File Key issues A Register is always 40 bits 40 bits wide
Top 32 bits used for integer Top 32 bits used for float 40 bits for precision float 32 registers available 16 at a time A Register is always 40 bits can be processed as a float can be processed as an integer Must convert integer<-> float 11/27/2018 ENCM Review of SHARC Processor Copyright

9 Sample ALU Instructions
SEE REF-CARD 11/27/2018 ENCM Review of SHARC Processor Copyright

10 ALU instructions -- Common errors
Key issues -- what IS NOT there rather than what IS there -- REMEMBER -- Superscaler RISC DSP CPU Rx = Ry + CONSTANT NOT THERE Rtemp = CONSTANT This twin instruction Rx = Ry + Rtemp MUST be used VERY COMMON TIME WASTER IN LABS WHEN NOT CHECKED NOTE: -- Rx = constant is not an ALU operation but an Immediate Move Universal Register instruction bringing in a value from PROGRAM memory as part of the op-code -- MOVEQ equivalent Ureg = <data32> 11/27/2018 ENCM Review of SHARC Processor Copyright

11 MAC instructions -- mainly INTEGER Multiply and Accumulate
SEE REF-CARD 11/27/2018 ENCM Review of SHARC Processor Copyright

12 Shifter Instructions -- mainly integer
SEE REF-CARD FPACK is a cast and means (32bit -> 16bit) Fx UNPACK is a cast and means (16bit -> 32bit) Rx BUT WITH A LOT OF HIDDEN STUFF TOO! 11/27/2018 ENCM Review of SHARC Processor Copyright

13 21061 ALU instructions Under the RIGHT conditions can do multiple operations at the same time Certain Ops using certain registers -- see reference material 1 MAC, 1 ALU (SOMETIMES 2), 1 SHIFTER ?, AND 1 DM ACCESS, 1 PM ACCESS Certain combinations can also be CONDITIONAL We are going to write code in a format that will allow us to parallel instructions -- an expectation for the course Depends on what you do and who you do it to (special registers combos) only a certain number of bits available in opcode (40 bits) so that not all reasonable combinations possible 11/27/2018 ENCM Review of SHARC Processor Copyright

14 REMINDER This is a FAMILIARIZATION lecture Learn a useful subset by OSMOSIS later on in course

15 21061 Memory Accesses Under the right conditions -- 3 memory accesses at same time Program Memory, Data Memory, Instruction Cache PLUS up to 3 Arithmetic operations at the same time 11/27/2018 ENCM Review of SHARC Processor Copyright

16 Data Address Generators -- DAG
DAG1 -- best for accessing Data memory (0 -- 7) DAG2 -- best for accessing Program memory ( ) MUST be used in this fashion for simultaneous memory ops Also an alternate set of DAGs 11/27/2018 ENCM Review of SHARC Processor Copyright

17 Register and Register Ops in DAG1
SPECIAL CIRCBUFFER STUFF SPECIAL FFT BIT 11/27/2018 ENCM Review of SHARC Processor Copyright

18 DAG register info Index registers Modify registers M0 -- M7, M8 -- M15
I0 -- I7 (dm -- data mem), I8 -- I15 (pm -- program mem) “like” 68K address registers A0 -- A6 Modify registers M0 -- M7, M8 -- M15 Can be offset registers (c.f 68K (4, SP) Can be used for high speed post increment Special Hardware for Circular Buffers Base registers B0 -- B7, B8 -- B15 Length registers L0 -- L7, L8 -- L15 See labs and associated lectures SEE REF-CARD 11/27/2018 ENCM Review of SHARC Processor Copyright

19 SHARC Universal Registers -- Ureg
SEE REF-CARD See first column of ENEL515 reference card KEY ISSUES -- Can do certain things to Ureg that you can’t do to other system registers 11/27/2018 ENCM Review of SHARC Processor Copyright

20 Some memory access instructions
SEE REF-CARD Add the following to your reference sheet ureg = <data32> 11/27/2018 ENCM Review of SHARC Processor Copyright

21 Special hardware addressing modes
SEE REF-CARD 11/27/2018 ENCM Review of SHARC Processor Copyright

22 Compute with Move instructions
SEE REF-CARD KEY ISSUES -- Multiple operations available in 1 instruction Compute, 1 dm access, 1 pm access PROVIDED you are describing memory operations using registers and not by a number -- dm(I1, 1) BAD -- dm(I1, M6) (with M6 = 1) GOOD MOST INSTRUCTIONS ARE CONDITIONAL (Why?) 11/27/2018 ENCM Review of SHARC Processor Copyright

23 SHARC Program Flow SEE REF-CARD Key issues
Condition affects ALL of the instruction, Compute and jump both become conditional JUMP and also JUMP (DB) 11/27/2018 ENCM Review of SHARC Processor Copyright

24 Delayed Branch -- A killer!
SEE REF-CARD 11/27/2018 ENCM Review of SHARC Processor Copyright

25 High Speed Loops available
Some possible HARDWARE loop operation instructions 11/27/2018 ENCM Review of SHARC Processor Copyright

26 You think you have it bad
Some recent architecture advances -- SISD, SIMD, VLIW Tiger SHARC CPU’s on the same chip -- working with the same instruction One CPU uses R registers and memory Moves using the value in the I register The other CPU uses S registers and memory Moves using the value in the I register PLUS 1 Hammerhead SHARC -- 2 CPU’s that can be independently controlled -- 8 possible operations in a single instructions 11/27/2018 ENCM Review of SHARC Processor Copyright

27 FLOATING & FIXED-POINT MULTIPLIER, FLOATING-POINT &FIXED-POINT ALU
* 07/16/96 TigerSHARC ADSP Core Architecture CACHE JTAG TEST & MEMORY EMULATION 32 x 48 FLAGS DAG 1 DAG 2 PROGRAM 8 x 4 x 32 8 x 4 x 32 SEQUENCER TIMER PMA BUS 32 FLOATING & FIXED-POINT MULTIPLIER, FIXED-POINT ACCUMULATOR REGISTER FILE 16 x 40 32-BIT BARREL SHIFTER FLOATING-POINT &FIXED-POINT ALU PMA DMA BUS 32 DMA PMD BUS 64 PMD BUS CONNECT DMD BUS 64 DMD REGISTER FILE 16 x 40 FLOATING & FIXED-POINT MULTIPLIER, FIXED-POINT ACCUMULATOR 32-BIT BARREL SHIFTER FLOATING-POINT &FIXED-POINT ALU *

28 Normal-Word - Dual Data - SISD
* 07/16/96 Normal-Word - Dual Data - SISD r0=dm(i0,m0), r4=pm(i8,m8) -- Like normal SHARC Memory Block 0 32-bit Word N3 32-bit Word N1 32-bit Word N2 32-bit Word N0 Memory Block 1 32-bit Word M3 32-bit Word M1 32-bit Word M2 32-bit Word M0 63 31 PM Data Bus DM Data Bus PEy Register File PEx Register File R0 R4 I0 points to normal word space in block 1 I8 points to normal word space in block 0 c. 11/27/2018 ENCM Review of SHARC Processor Copyright *

29 Long-Word - Dual Data - SISD
* 07/16/96 Long-Word - Dual Data - SISD r0=dm(i0,m0), r4=pm(i8,m8) bit precision Memory Block 0 Memory Block 1 32-bit Word M3 32-bit Word M1 32-bit Word M2 32-bit Word M0 Odd Address Even Address Odd Address Even Address 32-bit Word N3 32-bit Word N1 32-bit Word N2 32-bit Word N0 63 31 PM Data Bus DM Data Bus PEy Register File PEx Register File R0 R1 R4 R5 I0 points to long word space in block 1 I8 points to long word space in block 0 11/27/2018 ENCM Review of SHARC Processor Copyright *

30 Normal-Word - Dual Data - SIMD
* 07/16/96 Normal-Word - Dual Data - SIMD r0=dm(i0,m0), r4=pm(i8,m8) Memory Block 0 32-bit Word N3 32-bit Word N1 32-bit Word N2 32-bit Word N0 Memory Block 1 32-bit Word M3 32-bit Word M1 32-bit Word M2 32-bit Word M0 63 31 PM Data Bus DM Data Bus PEy Register File PEx Register File S0 R0 S4 R4 I0 points to normal word space in block 1 I8 points to normal word space in block 0 11/27/2018 ENCM Review of SHARC Processor Copyright *

31 Data Interleave for Multi-Channel Optimization
Instruction: vecprod: f8=f0*f4, f12=f8+f12, f0=dm(i0,m1), f4=pm(i8,m9); Up to 6 ALU Ops + 5 memory Memory Block 0 Memory Block 1 C[1] C[0] A[1] A[0] 0x50000 0x50002 0x50001 0x50003 Value Address Address Value 0x40000 0x40002 0x40001 0x40003 D[1] D[0] B[1] B[0] 63 31 PM Data Bus DM Data Bus PEy Register File PEx Register File S0 R0 S4 R4 I0 points to normal word space in Block 1 I8 points to normal word space in Block 0 11/27/2018 ENCM Review of SHARC Processor Copyright

32 Special instructions to handle “C”
Cjump -- getting to “C” compatible subroutine Processor architecture customized for C Replaces 3 instructions for faster operations Difficult to use in ENCM515 Will not be having assembly code calling other subroutines (95%) -- Why bother since slow! RFRAME -- returning to “C” environment Part of MAGIC lines of code See reference card 11/27/2018 ENCM Review of SHARC Processor Copyright

33 “C” interface to assembly code
SEE REF-CARD 11/27/2018 ENCM Review of SHARC Processor Copyright

34 21k Volatile registers when using “C”
SEE REF-CARD 11/27/2018 ENCM Review of SHARC Processor Copyright

35 Anticipated Errors while coding
SEE REF-CARD 11/27/2018 ENCM Review of SHARC Processor Copyright

36 Tackled today Reference sources Register file and operations
Memory configuration and operations Sample instructions Program Flow Some warnings of expected errors Code review and code review standards Some recent architectural advances Tiger-SHARC and Hammerhead-SHARC 11/27/2018 ENCM Review of SHARC Processor Copyright

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