1. Jeremy Reed jhr127@psu.edu
ATMEL AT24C512 2-wire Serial EPROM
Jeremy Reed

2. ATMEL AT24C512 2-wire Serial EEPROM
lectrically
rasable and
rogrammable
ead
nly
emory

3. ATMEL AT24C512 2-wire Serial EEPROM
• Low-voltage and Standard-voltage Operation
– 5.0 (V CC = 4.5V to 5.5V)
– 2.7 (V CC = 2.7V to 5.5V)
– 1.8 (V CC = 1.8V to 3.6V)
• Internally Organized 65,536 x 8
• 2-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Typical)
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
• 8-pin PDIP and 20-pin JEDEC SOIC, 8-pin LAP, and 8-ball dBGA TM Packages
Provides 524,288 bits of serial electrically erasable and programmable read only memory organized as 65,538 words of 8 bits each.

4. Block Diagram
Basic Block Diagram

5. Pin Description
Serial Clock (SCL): Input uses positive edge and output uses negative edge
Serial Data (SDA): Bidirectional for serial data transfer.
Device/Page Addresses (A1,A0): Device address inputs that are hardwired or left not connected for hardware compatibility. Defaulted to zero.
Write Protect(WP): GND=Normal write operations. Tied to Vcc=Write operations are inhibited. Defaulted to GND.

6. Absolute Maximum Ratings

7. DC Characteristics

8. Device Addressing
Requires an 8-bit device address word to enable the chip for a read or write operation
Eight bit determines read/write
High = Read
Low = Write

9. Write Operations
Two Types
Byte Write
Page Write

10. Byte Write Requires two 8-bit data word addresses EEPROM acknowledges
Clocks in the first 8-bit data word
Addressing Device must terminate write sequence
EEPROM enters write cycle

11. Page Write Capable of 128-byte page writes
Addressing Device does not terminate but transmits up to 127 more data words
Data word addresses are incremented internally following acknowledgement
Lower 7 bits incremented
Higher bits are not, maintaining the memory page row location
Will “roll-over” if more than 128 data words are transmitted

12. Three Read Operations Read Operations Current Address Read Random Read
Sequential Read

13. Current Address Read
Internal data word address counter maintains the last address accessed during last read/write operation, incremented by one
Device address is clocked in and acknowledged by EEPROM
Current address data word is clocked out

14. Random Read
Requires a “dummy” byte write sequence to load in data word address
Then current address read is initiated

15. Sequential Read Initiated by a current address read or a random read
Addressing device acknowledges
EEPROM continues to increment the data address and serially clock out the data words
Will “roll-over”
Addressing device generates a stop condition to finish

16. Xess XS40-010XL Can our bit files be stored on the AT24C512 chip?
Bit file is 35 KB
Converts to 286,720 bits
AT24C512 can store 524,288 bits