1. The architecture of PAL16R8

2. The architecture of PAL16R8

3. Comparison Between ROM,PLA and PAL
The Decoder(or AND array) implements all minterms
The AND array implements a limited no of Product terms
AND array is not programmable
AND array is programmable
OR array is programmable
OR array is not programmable
Additional inputs doubles the size of AND array
Additional inputs does not require doubling of size
It can implement SOP with any no of terms
It can implement SOP with limited no of terms
Costlier than PAL
Cheaper than PLA
Least flexible
Extremely flexible
Moderate flexible

4. Sequential Programmable Logic Devices (SPLDs)
AND-OR Array
(PAL or PLA)
Flip-Flops
Inputs
Outputs

5. Sequential Programmable Logic Devices (SPLDs)
PLDs consists of only gates. So only combinational circuit design is possible
SPLDs includes both gates and flip-flops. So sequential circuit design is possible
SPLDs are commercially avaible and vendor specific variant within each type
SPLDs includes flip-flops within the IC in addition to the AND-OR array
In SPLDs outputs can be taken from OR gates or from Flip-Flops

6. Sequential Programmable Logic Devices (SPLDs)
Field Programmable Logic Sequencer(FPLS) is the first SPLD
In SPLDs the flip-flops can be programmed to operate either JK or D Flip-Flop
Typical SPLD uses PAL together with D Flip-Flop
The PAL with Flip-Flops is referred as Registered PAL
The each section of SPLD is called as “Macrocell”
Macrocell consists AND-OR combinational logic function and optional Flip-Flop

7. Macrocell
CLK OE
I/P
O/P
MUX

8. The D Flip-Flop is edge triggered and changes state on clock edge
Macrocell
The D Flip-Flop is edge triggered and changes state on clock edge
The output of Flip-Flop is connected to Mux which is controlled by OE signal
The output of Flip-Flop is fed back to the input of the AND array
Typical SPLD has 8 to 10 Macrocells within one IC

9. Complex Programmable Logic Devices (CPLDs)
I/O BLOCK
I/O BLOCK
Programmable Interconnect Fabric
PLD
PLD
PLD

10. Complex Programmable Logic Devices (CPLDs)
Digital system design requires several PLDs
CPLD is a collection of individual PLDs on a single IC
CPLD consists multiple PLDs interconnected through Programmable Interconnect Fabric
IO Block provides connections to the IC
Each IO pin can be programmed to act as input or output
Each individual PLD contains typically 8-16 Macrocells
PIF directs the input to the individual Macrocell and similarly sent to output

11. Complex Programmable Logic Devices (CPLDs)
All Macrocells are fully connected. So the unused product term of one Macrocell can be used by near by Macrocell
Different CPLD vendors
ALTERA
AMD Mach 1-5
Xilinx XC 9500
Lattice and Cypress
The most commonly used CPLDs are ALTERA MAX 7000 Series and Xilinx XC 9500

12. Altera MAX 7000 series CPLD PIA Progr ammable Interconnect Array LAB
macrocells
I/O B L O C K
macrocells
I/O B L O C K
macrocells
macrocells
I/O B L O C K
I/O B L O C K

13. MAX 7000 CPLDs are high speed, low power and low cost devices
Altera MAX 7000 series CPLD
MAX 7000 CPLDs are high speed, low power and low cost devices
MAX 7000 CPLDs uses CMOS technology EEPROM memory cell
MAX 7000 consists array of
Logic Array Blocks
Programmable Interconnect Array
Programmable I/O Blocks
Each LAB has 36 inputs, 16 outputs and contains 16 Macrocells

14. PIA establishes connectivity between multiple LABs and I/O pins
Altera MAX 7000 series CPLD
PIA establishes connectivity between multiple LABs and I/O pins
I/O block establishes connectivity between I/O pins, PIA and LABs
GCLK and GCLRn connected to all macrocells
OE1n and OE2n connected to all I/O blocks to enable outputs
LAB outputs can be programmed to route from LAB to I/O pins
Outputs can be programmed to route from I/O block to PIA

15. Altera MAX 7000 Macrocell

16. Altera MAX 7000 series CPLD

17. XILINX XC9500 CPLD