1. Copyright 2006 - Joanne DeGroat, ECE, OSU
Timing & Concurrency I
How do you achieve deterministic concurrent simulation in a linear time world on a machine that is not inherently concurrent?
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

2. Overview – Timing & Concurrency
Basic digital circuit operation
Gate response
VHDL Concurrency
Process equivalency
Simulation example
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

3. Timing and Concurrency
“In an electronic circuit all components are always active and there is a timing associated with every element in the circuit.”
VHDL simulators implement a pseudo-concurrent environment to emulate this operation. VHDL was designed with simulation as a requirement and a pseudo-concurrent environment is formally defined and specified in the LRM.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

4. Copyright 2006 - Joanne DeGroat, ECE, OSU
Multithreading
Even with a multi-threaded architecture, any real architecture will be capable of supporting far less threads than the concurrency in a real circuit.
A formal paradigm is needed to emulate that concurrency under those conditions.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

5. Consider the following
Consider the digital circuit
In this example, all gates have a gate delay of 12 ns
Have input stimulus as shown and circuit is stable.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

6. Consider the following
At time t=0, input b transitions 1 to 0.
Then gates G1 and G2 respond for 12 ns
1/8/ L12 Timing & Concurrency
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7. Copyright 2006 - Joanne DeGroat, ECE, OSU
Result at 12 ns
At 12 ns G1 and G2 have transitioned their output and now G3 and G4 react
1/8/ L12 Timing & Concurrency
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8. Copyright 2006 - Joanne DeGroat, ECE, OSU
Result at 24 ns
At 24 ns G3 and G4 have transitioned their output
With change on G3’s output G4 will respond
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

9. Copyright 2006 - Joanne DeGroat, ECE, OSU
And now result at 36 ns
G4 response to transition on G3
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

10. Copyright 2006 - Joanne DeGroat, ECE, OSU
VHDL Concurrency
Within an architecture the order of concurrent statements is not significant.
The previous example becomes
ENTITY circuit_ex IS
PORT (a,b,c : IN BIT; z : OUT BIT);
END circuit_ex;
ARCHITECTURE concurrent OF circuit_ex IS
SIGNAL w,x,y : BIT;
BEGIN
w <= NOT b AFTER 12 ns;
x <= a AND b AFTER 12 ns;
y <= c AND w AFTER 12 ns;
z <= x OR y AFTER 12 ns;
END concurrent;
Each statement between begin and end translates into an independent process
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

11. Copyright 2006 - Joanne DeGroat, ECE, OSU
Notes on model code
Consider each statement (concurrent) such as
z <= x OR y AFTER 12 ns;
Represents an independent process
Whenever the value of a signal present on the rhs changes, the expression is evaluated and a transaction is generated that is a potential future value of z.
All forms of concurrent signal assignment statements are evaluated whenever an event occurs on a signal on the rhs.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

12. Copyright 2006 - Joanne DeGroat, ECE, OSU
More notes
When input b transitions from 1->0 anything “sensitive” to b is tagged for execution
Here G1 and G2 will be re-evaluated generating transactions
sig(val, abs time gen, delay time, action time)
x(‘0’, 0, 12ns, 12ns) -- From G2
w(‘1’, 0, 12ns, 12ns) -- From G1
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13. Copyright 2006 - Joanne DeGroat, ECE, OSU
Processes
The sensitivity list determines the signals to which a process is sensitive.
These two processes are equivalent, i.e., you could write it either way. THEY ARE THE SAME – BY DEFINITION.
1/8/ L12 Timing & Concurrency
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14. Copyright 2006 - Joanne DeGroat, ECE, OSU
The Processes
If a process has a sensitivity list it cannot contain any wait statements. A process that has without a sensitivity list can have any number of wait statements.
Notes on these processes.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

15. Concurrent signal assignment statement
Concurrent signal assignment statements have an equivalent process.
What is it?
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16. Concurrent signal assignment statement
Concurrent signal assignment statements have an equivalent process.
They are sensitive to the signals on the rhs.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

17. Concurrent signal assignment statement
And that process can be rewritten without the sensitivity list by using a wait statement.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

18. Copyright 2006 - Joanne DeGroat, ECE, OSU
Think about
Are these two equivalent?
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19. Copyright 2006 - Joanne DeGroat, ECE, OSU
Think about
Are these two equivalent? NO
The semantics of the process says that waits for 45 NS and then evaluates the equation, generating a new future value for X.
It then waits again for 45 NS not watching or responding to any transitions on Y, Z, or Q
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20. Copyright 2006 - Joanne DeGroat, ECE, OSU
Some definitions
Event
An event is said to occur on a signal when the current value of the signal changes as a result of the updating of that signal with its effective value.
Transaction
A transaction consists of a value and a time. The value part represents a (current or) future value of the driver; the time part represents the relative delay before the value becomes the current value.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

21. Copyright 2006 - Joanne DeGroat, ECE, OSU
The driver
Driver
A driver of a signal is a container for a projected output waveform. The signal’s value is a function of the current values of its drivers. Each process that assigns a value to a given signal implicitly contains a driver for that signal. A signal assignment statement affects only the associated drivers.
1/8/ L12 Timing & Concurrency
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22. Copyright 2006 - Joanne DeGroat, ECE, OSU
Sensitivity
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23. Copyright 2006 - Joanne DeGroat, ECE, OSU
Example
ARCHITECTURE demo OF example IS
SIGNAL a,b,c : BIT := ‘0’;
BEGIN
a <= ‘1’ AFTER 15 ns;
b <= NOT a AFTER 5 ns;
c <= a AFTER 10 ns;
END demo;
Look at what are the initial values and what transpires during simulaiton
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

24. Copyright 2006 - Joanne DeGroat, ECE, OSU
Example
At time t=0 have initial values of 0 on all three signals. This is assumed to be their stable value at time 0.
At time 0 you do an evaluation of all concurrent statements until they suspend.
A concurrent signal assignment state will evaluate the equation on the rhs and generate a transaction for its signal.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

25. Copyright 2006 - Joanne DeGroat, ECE, OSU
Here
At t=0
a <= ‘1’ AFTER 15 ns;
Generates the transaction a(‘1’,0ns, 15ns, 15ns)
b <= NOT a AFTER 5 ns;
a’s current value is ‘0’
Generates the transaction b(‘1’,0ns, 5ns, 5ns)
c <= a AFTER 10 ns;
Generates the transaction c(‘0’,0ns, 10ns, 10ns)
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

26. Copyright 2006 - Joanne DeGroat, ECE, OSU
Another view at t=0
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

27. Advance time till something to do
t=5ns
At t = 5 ns signal b will have the transaction on the event queue become its current value
But noting is sensitive to b and this event will simply change the value of b
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

28. Copyright 2006 - Joanne DeGroat, ECE, OSU
Again advance time
Next transaction has time 10ns
However, signal c already has value 0 so posting this transaction has no effect and does not result in an event.
Now advance to 15 ns.
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

29. Copyright 2006 - Joanne DeGroat, ECE, OSU
At 15 ns
Signal a has and event, changing value from ‘0’ to ‘1’
All concurrent statements sensitive to a are then re-evaluated
Here, that will be the other 2 statements, and result in generation of new transactions
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

30. Copyright 2006 - Joanne DeGroat, ECE, OSU
New Transactions at t=15
New transactions are
a’s current value is ‘1’
b <= NOT a AFTER 5 ns;
Generates the transaction b(‘0’,15ns, 5ns, 20ns)
c <= a AFTER 10 ns;
Generates the transaction c(‘1’,15ns, 10ns, 25ns)
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

31. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to 20 ns
Post b event but noting sensitive to b
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32. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to 25 ns
Post event on c but nothing sensitive to c
Simulation becomes quiescent
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU

33. Copyright 2006 - Joanne DeGroat, ECE, OSU
An exercise to try
Enter code of example and compile
Start simulation
Rather then ‘run all’ step the simulation by choosing the step option or entering “step” in the command window.
To view what is on the drivers in the command window enter:
>driver a
1/8/ L12 Timing & Concurrency
Copyright Joanne DeGroat, ECE, OSU