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ESE534: Computer Organization

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Presentation on theme: "ESE534: Computer Organization"— Presentation transcript:

1 ESE534: Computer Organization
Day 20: April 7, 2010 Interconnect 5: Meshes (and MoT) ESE Spring DeHon

2 Previously Saw need to exploit locality/structure in interconnect
a mesh might be useful Question: how does w grow? Rent’s Rule as a way to characterize structure ESE Spring DeHon

3 Today Mesh: Mesh-of-Trees (time permitting) Channel width bounds
Linear population Switch requirements Routability Segmentation Clusters Directional Wires Mesh-of-Trees (time permitting) ESE Spring DeHon

4 Mesh ESE Spring DeHon

5 Manhattan ESE Spring DeHon

6 Mesh switchbox ESE Spring DeHon

7 Mesh Strengths? ESE Spring DeHon

8 Mesh Channels Lower Bound on w? Bisection Bandwidth BW  Np
channels in bisection =N0.5 Channel width grows with N. ESE Spring DeHon

9 Straight-forward Switching Requirements
Total Switches? Switching Delay? ESE Spring DeHon

10 Switch Delay Switching Delay: Manhattan distance 2 (Nsubarray)
|Xi-Xj|+|Yi-Yj| 2 (Nsubarray) worst case: Nsubarray = N ESE Spring DeHon

11 Total Switches Switches per switchbox: 4(3ww)/2 = 6w2
Bidirectional switches (NW same as WN) double count ESE Spring DeHon

12 Total Switches Switches per switchbox: Switches into network:
(K+1) w Switches per PE: 6w2 +(K+1) w w = cNp-0.5 Total  w2N2p-1 Total Switches: N×(Sw/PE)  N2p ESE Spring DeHon

13 Routability? Asking if you can route in a given channel width is:
NP-complete ESE Spring DeHon

14 Linear Population Switchbox
ESE Spring DeHon

15 Traditional Mesh Population: Linear
Switchbox contains only a linear number of switches in channel width ESE Spring DeHon

16 Linear Mesh Switchbox Each entering channel connect to:
One channel on each remaining side (3) 4 sides W wires Bidirectional switches (NW same as WN) double count 34W/2=6W switches vs. 6w2 for full population ESE Spring DeHon

17 Total Switches Switches per switchbox: Switches into network:
(K+1) w Switches per PE: 6w +(K+1) w w = cNp-0.5 Total  Np-0.5 Total Switches: N×(Sw/PE)  Np+0.5 > N ESE Spring DeHon

18 Total Switches (linear population)
 Np+0.5 N < Np+0.5 < N2p Switches grow faster than nodes Wires grow faster than switches ESE Spring DeHon

19 Checking Constants (Preclass 2)
When do linear population designs become wire dominated? Wire pitch = 8l switch area = 2500 l2 wire area: (8w)2 switch area: 62500 w Crossover (2500 l2)? Crossover (5000 l2)? w=234 ? ESE Spring DeHon

20 Checking Constants: Full Population
Does full population really use all the wire physical tracks? Wire pitch = 8l switch area = 2500 l2 wire area: (8w)2 switch area: 62500 w2 effective wire pitch: 120 l ~15 times pitch ESE Spring DeHon

21 Practical Full population is always switch dominated Just showed:
doesn’t really use all the potential physical tracks …even with only two metal layers Just showed: would take 15 Mapping Ratio for linear population to take same area as full population (once crossover to wire dominated) Can afford to not use some wires perfectly to reduce switches (area) ESE Spring DeHon

22 Diamond Switch Typical switchbox pattern:
Used by Xilinx Many fewer switches, but cannot guarantee will be able to use all the wires may need more wires than implied by Rent, since cannot use all wires this was already true…now more so ESE Spring DeHon

23 Universal SwitchBox Same number of switches as diamond
Locally: can guarantee to satisfy any set of requests request = direction through swbox as long as meet channel capacities and order on all channels irrelevant can satisfy Not a global property no guarantees between swboxes ESE Spring DeHon

24 Diamond vs. Universal? Universal routes strictly more configurations
ESE Spring DeHon

25 Inter-Switchbox Constraints
Channels connect switchboxes For valid route, must satisfy all adjacent switchboxes ESE Spring DeHon

26 Mapping Ratio? How bad is it? How much wider do channels have to be?
detail channel width required / global ch width ESE Spring DeHon

27 Mapping Ratio Empirical: Theory/provable:
Seems plausibly, constant in practice Theory/provable: There is no Constant Mapping Ratio At least detail/global can be arbitrarily large! ESE Spring DeHon

28 Domain Structure Once enter network (choose color) can only switch within domain ESE Spring DeHon

29 Detail Routing as Coloring
Global Route channel width = 2 Detail Route channel width = N Can make arbitrarily large difference ESE Spring DeHon

30 Routability Domain Routing is NP-Complete
can reduce coloring problem to domain selection i.e. map adjacent nodes to same channel Previous example shows basic shape (another reason routers are slow) ESE Spring DeHon

31 Routing Lack of detail/global mapping ratio
Says detail can be arbitrarily worse than global Doesn’t necessarily say domain routing is bad Maybe can avoid this effect by changing global route path? Says global not necessarily predict detail Argument against decomposing mesh routing into global phase and detail phase Modern FPGA routers do not VLSI routers and earliest FPGA routers did ESE Spring DeHon

32 Buffering and Segmentation
ESE Spring DeHon

33 Buffered Bidirectional Wires
C Block S Block Logic Lemieux 2009

34 Segmentation To improve speed (decrease delay)
Allow wires to bypass switchboxes Maybe save switches? Certainly cost more wire tracks ESE Spring DeHon

35 Segmentation Segment of Length Lseg 6 switches per switchbox visited
Only enters a switchbox every Lseg SW/sbox/track of length Lseg = 6/Lseg ESE Spring DeHon

36 Segmentation Reduces switches on path N/Lseg May get fragmentation
Another cause of unusable wires ESE Spring DeHon

37 Segmentation: Corner Turn Option
Can you corner turn in the middle of a segment? If can, need one more switch SW/sbox/track = 5/Lseg + 1 ESE Spring DeHon

38 Buffered Switch Composition
ESE Spring DeHon

39 Buffered Switch Composition
ESE Spring DeHon

40 Delay of Segment ESE Spring DeHon

41 Segment R and C What contributes to? Rseg? Cseg?
ESE Spring DeHon

42 Preclass 3 What Lseg minimizes delay for: Distance=1? Distance=2?
ESE Spring DeHon

43 VPR Lseg=4 Pix ESE Spring DeHon

44 VPR Lseg=4 Route ESE Spring DeHon

45 Effect of Segment Length?
Experiment with on HW8 ESE Spring DeHon

46 Connection Boxes ESE Spring DeHon

47 C-Box Depopulation Not necessary for every input to connect to every channel Saw last time: K(N-K+1) switches Maybe use fewer? ESE Spring DeHon

48 IO Population Toronto Model IOs spread over 4 sides
Fc fraction of tracks which an input connects to IOs spread over 4 sides Maybe show up on multiple Shown here: 2 ESE Spring DeHon

49 IO Population ESE Spring DeHon

50 Clustering ESE Spring DeHon

51 Leaves Not LUTs Recall cascaded LUTs
Often group collection of LUTs into a Logic Block ESE Spring DeHon

52 Logic Block What does clustering do for delay?
[Betz+Rose/IEEE D&T 1998] ESE Spring DeHon

53 Delay versus Cluster Size
[Lu et al., FPGA 2009] ESE Spring DeHon

54 Area versus Cluster Size
[Lu et al., FPGA 2009] ESE Spring DeHon

55 Review: Mesh Design Parameters
Cluster Size Internal organization LB IO (Fc, sides) Switchbox Population and Topology Segment length distribution and staggering Switch rebuffering ESE Spring DeHon

56 Slides and Study from Guy Lemieux (Paper FPT2004 – Tutorial FPT 2009)
Only cursory coverage in lecture. See FPT 2004 paper (recommended reading). Directional Drive Slides and Study from Guy Lemieux (Paper FPT2004 – Tutorial FPT 2009) ESE Spring DeHon

57 Bidirectional Wires Problem Half of tristate buffers left unused
Buffers + input muxes dominate interconnect area Lemieux 2009

58 Bidirectional vs Directional
Lemieux 2009

59 Bidirectional vs Directional
Lemieux 2009

60 Bidirectional vs Directional
Lemieux 2009

61 Bidirectional Switch Block
Lemieux 2009

62 Directional Switch Block
Lemieux 2009

63 Bidirectional vs Directional
Switch Block Directional half as many Switch Elements Switch Element Same quantity and type of circuit elements, twice the wiring Lemieux 2009

64 Directional, Single-driver Benefits
Average improvements 0% channel width (most surprising?) 9% delay 14% tile length of physical layout 25% transistor count 32% area-delay product 37% wiring capacitance Any reason to use bidirectional? Lemieux 2009

65 Did not cover in lecture. See Journal article on recommended reading.
MoT Did not cover in lecture. See Journal article on recommended reading. ESE Spring DeHon

66 Recall: Mesh Switches Switches per switchbox: Switches into network:
6w/Lseg Switches into network: (K+1) w Switches per PE: 6w/Lseg + Fc(K+1) w w = cNp-0.5 Total  Np-0.5 Total Switches: N*(Sw/PE)  Np+0.5 > N Penn ESE Spring DeHon

67 Recall: Mesh Switches Switches per PE: Not change for
6w/Lseg + Fc(K+1) w w = cNp-0.5 Total  Np-0.5 Not change for Any constant Fc Any constant Lseg Penn ESE Spring DeHon

68 Mesh of Trees Hierarchical Mesh Build Tree in each column
[Leighton/FOCS 1981] Penn ESE Spring DeHon

69 Mesh of Trees Hierarchical Mesh Build Tree in each column
…and each row [Leighton/FOCS 1981] Penn ESE Spring DeHon

70 MoT Parameterization Support C with additional trees C=1 C=2
(like BFT) C=1 C=2 Penn ESE Spring DeHon

71 MoT Parameterization: P
Penn ESE Spring DeHon

72 Mesh of Trees Logic Blocks Connect to the C trees C<W
Only connect at leaves of tree Connect to the C trees Per side 4C total C<W Penn ESE Spring DeHon

73 Switches Total Tree switches Sw/Tree: 2 C N× (switches/tree)
Penn ESE Spring DeHon

74 Switches Only connect to leaves of tree Leaf switches: C(K+1)
Total switches Leaf + Tree O(N) Compare Mesh O(Np+0.5) Penn ESE Spring DeHon

75 Empirical Results Benchmark: Toronto 20 Compare to Lseg=1, Lseg=4
CLMA ~ 8K LUTs Mesh(Lseg=4): w=14  122 switches/LB MoT(p=0.67,arity=2): C=4  89 switches/LB Benchmark wide: 10% less CLMA largest Asymptotic advantage [Rubin,DeHon/FPGA2003] Penn ESE Spring DeHon

76 MoT Parameters C, P Arity Staggering Upper-Level Corner Turns
Leaf IO Population/topology ESE Spring DeHon

77 [Rubin&DeHon/TRVLSI2004]
Overall 26% fewer than mesh [Rubin&DeHon/TRVLSI2004] Penn ESE Spring DeHon

78 Admin HW8 due Monday Reading for Monday ESE Spring DeHon

79 Big Ideas [MSB Ideas] Mesh natural 2D topology
Channels grow as W(Np-0.5) Wiring grows as W(N2p ) Linear Population: Switches grow as W(Np+0.5) Worse than shown for hierarchical Unbounded globaldetail mapping ratio Detail routing NP-complete But, seems to work well in practice… ESE Spring DeHon

80 Big Ideas [MSB-1 Ideas] Segmented/bypass routes
can reduce switching delay costs more wires (fragmentation of wires) Hierarchy structure allows to save switches O(N) vs. W(Np+0.5) ESE Spring DeHon

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