1. Day 39: December 5, 2014 Repeaters in Wiring
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 39: December 5, 2014
Repeaters in Wiring
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2. Previously Transmission line (LC wire) wire delay scales as Length
Unbuffered RC wire delay scales as Length2
0.5 Rwire Cwire
0.5 L2 Ru Cu
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3. Today RC (on-chip) Interconnect Buffering
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4. (on-chip, no inductance, L)
Back to RC Wire
(on-chip, no inductance, L)
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5. Delay of Wire Long Wire: 1mm Ru = 60K W per 1mm of wire
Cu = 0.16 pF per 1mm of wire
Driven by inverter
R0 = 25K W
C0 = 0.01 fF
Assume velocity saturated, sized Wp=Wn=1
Loaded by identical inverter
Roughly 22nm from ITRS 2008 INTC2 (in FOCUS_B tables)
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6. Formulate Delay Delay of inverter driving wire?
Should be able to do these calculations on final.
Formulate Delay
Delay of inverter driving wire?
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7. Calculate Delay Cload = 2 C0 Rbuf = R0 Cself = g 2 C0 = 2 C0
9ns .. 4ns in Rbuff*Cwire, 5ns in Rwire*Cwire
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8. Buffering Wire
Complete Preclass Table
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9. N Buffers
Delay Equation for N buffers?
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10. Minimize Delay How determine N to minimize delay?
Derivative with respect to N
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11. Solve for N
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12. Minimize Delay Equalizes delay in buffer and wire
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13. Calculate: Delay at Optimum Stages for Example
Ru = 60K W per 1mm of wire
Cu = 0.16 pF per 1mm of wire
Rbuf=R0 = 25K W
Cself=Cload=2(C0 = 0.01 fF)=0.02fF
N=56 or each stage is about 18um long
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14. Segment Length Rwire = L×Runit Cwire = L×Cunit
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15. Optimal Segment Length
Delay scales linearly with distance once optimally buffered
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16. Buffer Size? How big should buffer be? Rbuf = R0/W
Cload = 2 W C0 (assuming velocity saturation)
Cself = g 2 W C0
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17. Implication W Rwire = L×Runit Cwire = L×Cunit
 W independent of Length
Depends on technology
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18. Delay at Optimum W With g=1, 1+g=2 Same size as first term
So, about 169ps*2 ~=340ps
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19. Ideas Wire delay linear once buffered Optimal buffering matches
Buffer delay
Delay on wire between buffers
Delay of wire driving buffer
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20. Final Everything Focus on wiring, memory Delay Energy Static CMOS
Including today
Focus on wiring, memory
Crosstalk
Transmission lines
Delay
Energy
Static CMOS
Precharge
Pass Transistors
Ratio
Clocking
Restoration
Buffering
2010, 2011, 2012, 2013 finals all good content
many “small” problems – good coverage
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21. Admin Ron Review Monday (12/8) Final (12/18) noon Towne 303
Talk with him about final Q&A session
Final (12/18) noon Towne 303
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