1. SAT-Based Area Recovery in Technology Mapping
Alan Mishchenko
Department of EECS
UC Berkeley

2. Overview SAT-based technology mapping
SAT vs. other computation engines
Experimental results 2

3. SAT-based Structural Mapping
Input the original mapped circuit and the library
Iterate over small multi-output cones (10-20 gates each) in some order
Convert the cone into an AIG
Compute cuts and matches for each AIG node using the library
Describe the set of all structural gate covers of the cone as a CNF
Introduce one SAT variable for each node polarity and for each cut
If a node is used in the mapping, it implies that one of its cuts is used
If a cut is used, it implies that the root and the leaf nodes are used
The output nodes should be used in the mapping
Cardinality constraint limits the gate count
Solve incremental SAT
Incrementally reduce solution cardinality if needed
Timing constraints are handled as a SAT solver callback
If there is an improvement, replace original mapping of the cone by the new one
Output an improved circuit

4. CNF / Mapping Terminology
CNF is composed of variables, literals, and clauses
Each variable represents some aspect of the problem
Each literal is a variable in positive or negative polarity
Each clause is a disjunction of literals
CNF is a conjunction of clauses
Mapping is a set of gates completely covering the subject graph
Internal nodes of the subject graph can be
Used in the mapping (if mapping includes a gate rooted in this node)
Not used in the mapping (otherwise)
Gate cover represents a valid mapping if
Internal nodes driving the circuit outputs are used in the mapping
For each gate, its inputs are used in the mapping or are primary inputs

5. CNF for Structural Mapping
Disclaimer! This is a simplified formulation of standard-cell mapping
assumes one variable per node (rather than two variables for each polarity)
CNF variables
one variable (ni) for each node
ni is 1, iff node i is used in the mapping
one variable (cik) for each match (cut + gate) of the node
cik is 1, iff match k is used to map node I
CNF clauses
ni  k (cik) (If a node is used, one of its matches is used)
cik  f (nf) (If a match is used, all cut fanins are used)
o (no) (The nodes driving the outputs are used in the mapping)
i ni ≤ Limit (The gate count does not exceed the known mapping)

6. Handling of Timing Constraints
Timing constraints can be simplified (discretized) and turned into CNF
However, this leads to an increase in CNF size and a slowdown in solving
A better way to handle such constraints, is to use a dedicated constraint propagation engine (in this case, a timer)
SAT solver and the timing engine interact similar to how SMT solver is built around a SAT solver and one or more domain solvers
SAT solver leads the constraint propagation and passes partial assignments to the domain solvers, which propagate them on the domain constraints and return learned clauses to SAT solver
In the context of a technology mapping, it means that SAT solver finds valid structural mappings, repeatedly evaluated by the timer
If the timer finds that the mapping meets the timing, a solution is found
Otherwise, the timer returns the critical path, which is interpreted as a blocking clause by the SAT solver
The SAT solver continues to explore the search space until it either
Finds a mapping that satisfying the timing
Returns UNSAT after exploring all valid mappings
Runs out of resources (runtime, memory, etc)

7. Experimental Results
Please refer to the following paper

8. SAT vs. Other Computation Engines
The presented computations can be implemented with any engine
SAT, BDDs, SOPs, truth tables, etc
The implementations differ greatly in terms of
Complexity
Resource usage
Quality of results
Scalability
Based on these metrics, SAT-based implementations are rated highly
Relatively easy to implement (using an off-the-shelf solver)
Relatively inexpensive (both memory and runtime requirements are reasonable)
Good quality of result (typically, there is no clear win against other method)
The most scalable among known engines (this is the main advantage!)
The main reason why SAT is more scalable than BDDs
BDDs require construction of a canonical form before they can be used
CNF construction is linear; so, SAT starts working on the problem right away
As a result, SAT has more chances to solve a hard instance of an NP-hard problem

9. Conclusion Introduced the SAT solver as a Boolean computation engine
Discussed structural mapping based on SAT
Discussed the key difference of SAT and BDDs
And why SAT replaced BDDs in most applications

10. Abstract
This work proposes a new SAT-based algorithm for recovering area in technology mapping. The algorithm considers a sequence of relatively small overlapping regions of a mapped network and computes an improved mapping of each using a SAT solver. Delay constraints are taken into account by interfacing the SAT solver with a timer. Experimental results are given for mapping into 6-LUTs. An average reduction in area on top of a high-effort area-only synthesis/mapping flow was 3-4% while for some benchmarks the area reduction was more than 10%.