1. Hybrid Architecture of DCT/DFT/Wavelet Transform (HWT)
EE 800
Hybrid Architecture of DCT/DFT/Wavelet Transform (HWT)
Project Name:
Md. Ashraful Islam
Samia Sharmin Shimu

2. Objective
Hardware implementation of Hybrid Discrete cosine transform (DCT) / Discrete Fourier Transform (DFT)/Wavelet Transform (HWT) in single chip.

3. Motivation Combine three different transformation method in one chip
Hardware saving
Less Power consumption

4. Methodology
The Algorithm of combining DCT/DFT/HWT is obtained from the paper, Zhu Chen, Moon Ho Lee “On Fast Hybrid Source Coding Design”, 2007 International Symposium on Information Technology Convergence.
The coefficient matrix of DCT, DFT and Haar wavelet are structured in similar pattern to share the common block diagrams.
Different combination of matrix algorithm has been use to decompose the classical DCT,DFT and Haar matrix to find out the common blocks which will be shared by the three filters in our architecture.
Hardware implementation would be done by Verilog.

5. Butterfly data flow diagram of N-by-N DCT II

6. Butterfly data flow diagram of N-by-N DFT

7. Butterfly data flow diagram of N-by-N HWT

8. Application
Signal and image processing, Video data compression can be performed by this hybrid chip using DCT/DFT/ HWT.

9. Question?

10. Thanks