1. Impact of Serializer/Deserializer Architecture on ETD High-Speed Links
A. Aloisio, R. Giordano
In this talk
Physics Dept. - University of Napoli “Federico II”
and INFN Sezione di Napoli, Italy

2. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Outline
Links in the ETD architecture
Link Mezzanine
On-detector end of the links
Comparison between two off-the-shelf SerDes candidates for on-detector application
Future work
Conclusions
28/11/2018
Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

3. ETD: overall system architecture
From: D.Breton –
ETD session –
SLAC SuperB Workshop – October 2009
FCTS: Fast Control and Trigger System
ROM: Read Out Module
FPGA-to-FPGA Links (A-Type)
FPGA-to-SerDes
Links (B-Type)
SerDes-to-FPGA Links (C-Type)
Identified 3 types of links:
A-Type: both ends off-detector (FPGA-FPGA)
B-Type: source off-detector (FPGA-embedded) destination on-detector (discrete SerDes)
C-Type: source on-detector (discrete SerDes) destination off-detector (FPGA-embedded)
Implemented and successfully tested A-Type and B-Type links, C-Type Links under development
28/11/2018
Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

4. Advantages of a Modular Approach
How should we implement the links?
Serial links could be implemented on a plug-in mezzanine board
Advantages:
Easy upgrade of Serial Links
performance (datarate, power, jitter)
replacement (chip-sets may become obsolete)
Decouple links from logic
Single ‘authority’ to certify performance, specs, characterization
Critical link issues (latency, jitter) only in a sub-block
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

5. Advantages of a Modular Approach (2)
Moreover:
‘One board fits all’
Design effort focused on a ‘critical but single’ board
Common Interface (to be discussed)
Single PCB customized with different components to fit different needs (e.g. jitter cleaners)
Optimal design methodology
Parallelism (other ETD components might be designed in the meanwhile)
Job done just once, only one team will need to cope with link complexity
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

6. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
B-Type Links (tested)
Seed Clock
(frefclk ±5%)
SerDes
National DS92LV18 has fixed-latency, candidate to be radiation tolerant
Line rate at 1.25 Gbps, limited by DS92LV18
Successfully completed tests for FPGA-to-National transmission
Latency fixed
Jitter needs to be measured
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

7. C-Type Links (under development)
FPGA-side implementation under development
On-detector SerDes could be
National DS92LV18 (fixed-latency, same phy-layer and coding of Type B links, 1.25 Gbps => more links needed)
Texas TLK2711A (variable latency, 8b10b coding, 2.5 Gbps)
Let us analyze the impact of the architecture of those components on the on-detector side of the links
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

8. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Power Supply
National DS92LV18
Needs 3.3 V
separate power for PLL, analog, digital (every 4 IO pins)
Power separation may improve jitter in PLL (could mean clean clock delivered by FCTS)
Texas TLK2711A
Needs 2.5 V
separate power for analog and digital
PLL very likely shares power with analog circuitry (could mean dirtier clock delivered)
Jitter must be measured for both devices
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

9. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Clocking
National DS92LV18
clock range: 15 to 66 MHz => experiment clock at MHz can be used
Texas TLK2711A
Clock range: 80 to 135 MHz => experiment clock needs to be multiplied externally (56-60x2 MHz), more components, more jitter injected in stream
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

10. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Encoding
National DS92LV18
Non-standard, custom coding, not dc-balanced
20-bit symbol, 18-bit payload (10% overhead)
Need external logic coding for dc-balancing (e.g. payload scrambler) => additional overhead (how much ?)
S. Cavaliere (INFN-Napoli) working on encodings to ensure both dc-balance and FEC
Texas TLK2711A
Standard, 8b10b, excellent dc-balance
20-bit symbol, 16-bit payload (20% overhead)
Additional overhead for FEC (how much?)
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

11. CDR Locking and Alignment
National DS92LV18
seed clock frequency must be within ±5% of transmitter clock frequency (easy to achieve with cheap xtal)
Lock pattern and sync procedure
Lock flag (pin indicating lock correctly achieved)
Texas TLK2711A
Seed clock frequency within ±200ppm of transmitter clock frequency (little harder than DS92LV18, but still easy)
Link lock based on 8b10b comma characters
No lock flag, external logic needed to decide if lock has been achieved
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

12. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Self Testing
National DS92LV18
PRBS generation
2 loopback modes:
parallel section testing
Full datapath testing (connects serial input to serial output)
Texas TLK2711A
Full datapath testing
Automatic BIST procedure, a pin flags the result of the test
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

13. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Future Work
Qualify radiation hardness of National DS92LV18 and Texas TLK2711A (since they are candidates to be on-detector)
National DS92LV18 suitable for deployment on Type C links
Test transmission from National DS92LV18 to FPGA
Implement FPGA-side of serial links for data read-out (mezzanine for ROMs)
Define a common interface for the mezzanine (depends also on FCTS requirements). In particular set:
Bus size (32-bit?)
Clock frequency (56 MHz?)
Number of links per board (1?)
Signaling (TTL,LVDS, LVPECL?)
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

14. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Conclusions
National DS92LV18
fixed latency (tested in lab) but slower data-rates (1.25 Gbps) => appealing for FCTS mezzanines (where data-rate not critical and fixed latency needed)
Texas TLK2711A
variable latency but higher data-rates (2.5 Gbps) => appealing for readout on-detector side (where fixed latency not needed and higher data-rate desired)
Both devices need external components (FPGA, PLL), in order to provide FCTS signals reliably
DS: dc-balance of the payload
TLK: alignment, PLL for experiment clock multiplication
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

15. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Back-up Slides
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

16. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
Modular Approach
Cons:
Connector, yes but
Very good connectors available for SI and perf.
More usable surface on board
Cost (FPGA and one board more), yes but
Board less complex, easier test
Suboptimal use of FPGAs (not all resources occupied), yes but
Deployment of FPGAs optimized for Serial IO
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009

17. Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009
A-Type Links (tested)
Embedded SerDes
FPGA to FPGA (Xilinx V5 with embedded SerDes, the GTP)
GTP has not fixed latency by default, we added specific logic in the fabric to achieve it
Encoding/Decoding external, GTP working as a SerDes only
Jitter measurements and latency tests performed with reference clock 62.5 MHz, 32-bit parallel bus, SerDes clock at 250 MHz, line rate 2.5 Gbps
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Raffaele Giordano - XI SuperB Workshop, Frascati Dec. 1st-4th 2009