Download presentation
Presentation is loading. Please wait.
1
Future trends in nano-CMOS cell design
2
WHERE DO I COME FROM
3
Founded in -120 B.C by romans
TOULOUSE, FRANCE Founded in -120 B.C by romans Best place to study in France Airbus A380 Cassoulet Rugby
4
CONTENTS General trends Technology Trends About Microwind FinFET implementation Design for manufacturability The educational dilemma Link to Research Conclusion
5
1 GENERAL TRENDS
6
INDUSTRY CURRENT CHANGES
Meeting the Industrial 4.0 challenge : cyber-physics systems Productivity, Efficiency, Safety, Connectivity
7
Electronic Market Growth
Share of system sales 2020 vs 2015 VISION 2020 Increasing disposable income, Expanding urban population, Growing internet penetration and Availability of strong distribution network Smartphones Internet of Things PC TV Automotive Tablets Game consoles Medical Servers -10% Growth 10% 20% Electronic Market Growth
8
Year THE ELECTRONIC MARKET GROWTH Market Growth Individuals 30%
Companies 4G IoT ADAS PC at home Internet GSM MP3 DVD Flat screens Automotive HDTV 3G Society 20% PC in companies Audio CD Defense Local Energy Security Medical 4% 2018 10% Recession Bank crash 4% 2017 Recession -10% Telecom crash 83 86 89 92 95 98 01 04 07 10 13 16 19 Year Adapted from Electronique International Mai 21, 2009
9
Crypto, sensor, position processor
TECHNOLOGY TRENDS TOWARDS TERA DEVICES 14nm 2016 4G+ Today Octa Core Multi DSP 3D 4K Image Proc Crypto, sensor, position processor Agregated RF 2 Gb Memories 15G 5nm 150 G 2020 ? 5G Technology 130nm 90nm 45nm 28nm Complexity 250M 500M 2G 7G Packaging Mobile generation 3G 3G+ 4G 2004 2007 2010 2013 Core DSPs 10 Mb Mem Dual core Dual DSP RF Graphic Process. 100 Mb Mem Sensors Quad Core Quad DSP 3D Image Proc Crypto processor Reconf FPGA, Multi RF 1 Gb Memories Multi-sensors Embedded blocks
10
MOBILE SUBSCRIBERS 4G 3G 2G Mobile Business
We are here 4G 3G 2G
11
https://gsmaintelligence.com/
MOBILE SUBSCRIBERS June 2018 .. Oct 2014 (-3 years)
12
INTERNET OF THINGS
13
TOWARDS AUTOMATIC DRIVE
ADAS TOWARDS AUTOMATIC DRIVE 2020 : Injury-free driving 2030: Accident-free driving ? 2040: Autonomous driving?
14
2 TECHNOLOGY TRENDS
15
https://en.wikipedia.org/wiki/Transistor_count
TOWARDS 100 GT 10 GT in 2015 8-bit 64-bit Multi-core 16 bit 32 bit Dual core Quadcore 1 GT in 2010 50 GT in 2018
16
FINFET MOSFET GAAFET TECHNOLOGY TRENDS MOS Current drive (mA/µm) 2.5
FinFET for increasing drive current and reducing leakage Gate All Around FET MOS Current drive (mA/µm) High K Metal Gate to increase field effect Strain to increase mobility High performance 2.5 FINFET 2.0 General Purpose MOSFET 1.5 Low power Ioff: 100nA/µm 1.0 10nA GAAFET 1 nA 0.5 0.0 130 45 65 90 10 20 32 14 7 5 3 Technology node (nm) Intrinsic perf. Gate material Strain
17
Samsung Exynos 8895 in 10-nm (2017)
TECHNOLOGY TRENDS IBM, GlobalFoundries, Samsung, SUNY first 7-nm testchip (2017) Samsung Exynos 8895 in 10-nm (2017) Qualcomm Snapdragon X50 in 10-nm (2017) Imec & Cadence first 3-nm testchip (2018)
18
Data Rate per pin (Gb/s)
CURRENT CHANGES Technology Faster and faster memory DDR4, LPDDR is on the market DDR5, LPDDR5 is under development DDR4: 250ps 2010 Laptop Memory 2012 2014 2016 2018 2020 Data Rate per pin (Gb/s) DDR3 DDR2 1 Gb/s 10 Gb/s 100 Gb/s WideIO LPDDR2 LPDDR3 DDR4 LPDDR1 Mobile Memory WideIO2 LPDDR4 DDR5 We are Here 3D 2D
19
SUPPLY VOLTAGE SCALE DOWN
The supply is lowered below 1V 14-nm technology Supply (V) 5.0 0.8 V inside, 1.2V outside 3.3 I/O supply 2.5 Core supply 1.8 1.2 1.0 0.35µ 0.18µ 130n 90n 65n 45n 32n 20n 14n 10n 7n Technology node
20
Technology CURRENT CHANGES
2.5D high bandwidth and high density DRAM with TSV and Si Interposer 1 tera-bit/cm2 achieved 5 years ahead from roadmaps We are Here
21
65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm SCALE DOWN BENEFITS
Smaller Faster Less power consumption Cheaper (if you fabricate millions) 65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm
22
SCALE DOWN BENEFITS Maximum die size One Core One core AMD dual core 65nm Intel Octa core 22nm 8 cores instead of 1 using the same space 3 times faster 10 times less power consumption
23
High-K, low-K dielectric, Airgap Metal gate FinFET
TECHNOLOGY INNOVATION & COST Strain, eSiGe, High-K, low-K dielectric, Airgap Metal gate FinFET Double, quad patterning
24
TECHNOLOGY TRENDS TOWARDS BILLION $ FAB
25
TECHNOLOGY INNOVATION & COST
Less and less companies in the 14-nm market 3 companies in 10-nm market 3 companies in 7-nm? 2 companies in 5-nm? Keynote_Ajit Manocha_GLOBALFOUNDRIES
26
ULTIMATE NANO CMOS Synopsys sketched out a generic roadmap to 2 nm
27
Processor die GOING 3D THERE IS PLENTY OF SPACE ON THE TOP
3D technology uses stacked dies, through-silicon-vias Enables Gb/s/pin at 1.0V Samsung 3D (Galaxy 6) vs PoP (Galaxy 5) : 30% faster 20% less power Less heat Thinned memory die 10 µm Multicore 350 µm thickness Direct bond interconnect (DBI) Package leadframe (GND) Through Silicon Via (TSV) Possible 3rd die Bottom die Upper die
28
Hybrid Memory Cube (HMC) High Bandwidth Memory (HBM)
3D IC TECHNOLOGY Hybrid Memory Cube (HMC) High Bandwidth Memory (HBM) Adaptive Compute Acceleration Platform (ACAP) Everest from Xilinx Industry’ first 50 GT November 18
29
EUROPRACTICE ACTIVIT REPORT 2017
ACADEMICS DONT LIKE NANO-CMOS Most adacemic designs in 2017 were made in 0.18µm & 0.35µm Still a lot of innovation possible (IoT, smart sensors, etc.) 0.35µm 0.18µm 1 65 nm 2 3 EUROPRACTICE ACTIVIT REPORT 2017
30
3 ABOUT MICROWIND
31
www.microwind.org WHAT IS MICROWIND
Microwind is a unique educational tool for designing nano-CMOS cells Microwind may be configured in any technology from 1.2µm downto 5 nm Microwind illustrates 2D, 3D aspects of Ics Microwind simulates cells & blocks using embedded simulator
32
Acceptable for simulators
MOS MODELS Microwind uses Level1, Level3, and a simplified version of BSIM4, adapted to MOS, FinFET and GAAFET “Typically, FinFET models have over 1,000 parameters per transistor, and more than 20,000 lines of C code” BSIM in Microwind uses 25 parameters and 250 lines of code… but makes many simplifications Bsim CMG Bsim6 Acceptable for simulators 1000 Bsim4 Bsim3 Bsim2 Bsim Model parameters 100 MM9 Level 2 Level 3 Acceptable for teachers 10 Level 1 Acceptable for students 1 1970 1980 1990 2000 2010 2020 Year
33
MICROWIND FEATURES FOLLOWING THE SCALE DOWN 2 supply Low K Double patterning Metal gate nMOS Strain Pocket implant pMOS Strain High K oxide 8 Metal Double gates
34
2nd generation strain, 10 metal layers
NANO-CMOS APPLICATION NOTES Made in Ecuador Technology node Year of introduction Key Innovations 90nm 2003 SOI substrate 65nm 2004 Strain silicon 45nm 2008 2nd generation strain, 10 metal layers 32/28nm 2010 High-K metal gate 20nm 2013 Replacement metal gate, Double patterning, 12 metal layers 14nm 2015 FinFET 10nm 2017 7nm 2019 5nm 2021 GAAFET > Application Notes
35
www.microwind.org > Application Notes > soon coming
NANO-CMOS APPLICATION NOTES MOS FET FIN FET GAA FET IBM’s GAA FET > Application Notes > soon coming
36
3-STAGE RING OSCILLATOR
LL : 190 GHz 0.12 mW VDD = 0.80V HS: 204 GHz 0.15 mW VDD = 0.80V HS Max : 230 GHz 0.27 mW VDD = 0.90V
37
3-STAGE RING OSCILLATOR
At same power dissipation, the oscillation is 4 times faster FinFET Speed x 4 at same power Power /3 at same speed MosFET High speed Low leakage
38
4 INTRODUCING THE FINFET
39
MICROWIND FINFET Microwind’s FinFET implementation based on a selection of 10 scientific publications The FinFET is used starting 14-nm node Layout, size and performances inspired from “average” 14-nm FinFET Scaling to 10-nm & 7-nm nodes Application note in progress Standard cell level parasitics assessment in 20nm BPL and 14nm BFF P. Schuddinck, IEDM 2012 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits Ajay N. Bhoj, IEEE VLSI, Vol 21, N°11, 2013
40
The FinFET device has a different layout style than the MOS device
FROM MOSFET TO FINFET >= 20nm <= 14nm The FinFET device has a different layout style than the MOS device Instead of a continuous channel, the FinFET uses fins FinFET provides the same Ion current at a smaller size FinFET provides lower leakage current Ioff at the same Ion fins
41
3D OF FINFET USING MICROWIND
Microwind enables a 3D view of the FinFET P-FinFET Fin 4 Drain Fin 3 Fin length (LG) Fin 2 Fin thickness (TF) Source Fin 1 Fin height (HF) Gate N-FinFET
42
FIN from Drain to Source Total equivalent channel width Weq
FIN BENEFITS Fin thickness (TFIN) The total equivalent channel width is higher in FinFET than in MOSFET Weq = 2*HFIN+TFIN Benefit around 30% in current drive Gate Fin height (HFIN) FIN from Drain to Source Total equivalent channel width Weq MOS Fin Ioff Patton, Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D, IEEE International SOI Conference 2012 Ion
43
GENERATING A FINFET HD: High density drawing style : 2 fins HP : High performance drawing style : 4 fins 1 fin exists in very high density cells such as SRAM FinFET with more than 4 fins drive string currents
44
5 DESIGN FOR MANUFACTURABILITY
45
Ion Ion Ioff Ioff FINFET MANUFACTURABILITY
Fins should be aligned and horizontal, regular pitch 6 (1+5) Non-aligned fins may lead to gate distortion and current performance spread Ion Ion Ioff Ioff
46
FINFET MANUFACTURABILITY
Gates should be aligned and vertical, regular pitch with 8 minimum (2+6)
47
With 2 fins, Weff=140nm FINFET MODEL
BSIM4 is a good model for MOS devices BSIM-CMG is targetted to FinFET, but corresponds to a completly new model The HFIN and TFIN parameters have been added to BSIM4 in Microwind to handle the FinFET HFIN: Fin Height TFIN: Fin thickness Fin thickness (TF) 10nm With 2 fins, Weff=140nm Fin height (HF) 30nm
48
Main target Pitch nm Used for M7, M8 4 24 192 Supply M5, M6 3 18 144
INTERCONNECTS Metal stack Main target Pitch nm Used for M7, M8 4 24 192 Supply M5, M6 3 18 144 Long routing M3, M4 2 12 96 Medium routing M1, M2 1.4 8 64 Short routing Gate, Local interc. 1 6 48 Intra-cell routing
49
Nearly manufacturable Not manufacturable
STUDENT DESIGNS Nearly manufacturable Not manufacturable ALU project by Master students INSA, 2016 SRAM project by Master students INSA, 2016
50
Simple, Double, Quadruple (and so does the cost..)
PATTERNING Simple, Double, Quadruple (and so does the cost..) Pitch (nm) λ >120 110 100 90 80 70 60 50 40 30 20 Patterning Single Double Quad 45-nm All 32-nm 18 M3-M8 M1-M2 Gate 20-nm 12 M7-8 M5-M6 M3-M4 14-nm 8 10-nm 6 7-nm 4 SINGLE DOUBLE QUADRUPLE Complexity Integration
51
6 MASTER OF NANOELECTRONICS
52
Master in Nano-Electronics
GENERAL OBJECTIVES Master in Nano-Electronics Created by Prof. Lionel TROJMAN, USFQ Objective: To Form professional with knowledge in Nano-electronics for international industrial application … To forge skills of investigation, production and development of modern technology To promote enter business, innovation and focus attitude to the device technology evolution
53
16 modules, 11 international professors
PROGRAM 16 modules, 11 international professors Michel Doisy (INPT) Analysis and signal processing 1 Frederic Surre (CUL) Analysis and signal processing 2 Luis-Miguel Procel (USFQ) Fundamental Physics 2: Electromagnetism Edgar Carrera (USFQ) Fundamental Physics 1: Quantum mechanics and Statistical Physics Lionel Trojman (USFQ) Semiconductor Physics Analog CMOS Technology: Fundamental circuit & NL electronic Nathalie Raveu (INPT) HF Electronics 1: Network Analysis and transmission line Digital CMOS technology 1: DSP Dragos Dancila (UU) HF Electronics 2: Matching Impedance and microwave resonator Marco Lanuzza (UNICAL) Digital CMOS Technology 2: Basic and perspective design Julien Perchoux (INPT) Optoelectronica 2: LASER and DEL Ivo Rendina (UNICAL) Optoelectronica 1: Optical fiber Adam Quotb (INPT) Chip Design 1: FPGA and VHDL Felice Crupi (UNICAL) Nanometric device 2: nano scaled devices, characterization and modelling Etienne Sicard (INSA) Chip Design 2: Microprocessor and memories design (ASIC) Laurent Raymond (IM2NP) Nanometric device 1: nanostructure and nanomaterial
54
DESIGN OF AN ASIC IC Design – part 1 : Design of an Asic nMOS, pMOS switch Inverter, ring oscillator Basic gates XOR gate Adder/Substract Latches & counters Embedded memories Analog OpAmp
55
Clock divider – Sofia Lara
DESIGN OF AN ASIC BASIC BLOCS 40 GHz oscillation Esteban Jose Clock divider – Sofia Lara
56
4-bit adder – Diego Jaramillo 4-bit counter – Luis Sanchez
DESIGN OF AN ASIC ARITHMETICS 4-bit adder – Diego Jaramillo 4-bit counter – Luis Sanchez
57
4-bit adder – Jose Felix Chavez
DESIGN OF AN ASIC ARITHMETICS 4-bit adder – Jose Felix Chavez 4-bit counter – Carlos Macias
58
DESIGN OF AN ASIC IC Design – part 1 : Design of an Asic PILS project Create a full chip Solve interfacing issues Connect ALU, clock, Ios, Memory together Try to synchonize all parts Present the results Write an IEEE-charted report
59
CONCLUSION
60
CONCLUSION The electronic market growth should be driven by 5G mobile, automatic drive, Internet of Things, etc. The trends towards 7nm technology have been described Microwind is a unique educational tool in nano-CMOS design, with scalability to 5 nm The Master in Nanoelectronics has been setup to form professional with knowledge in Nano-electronics ASIC parts designed by students
61
Thank you for your attention
Thanks to the audience Thanks to Lionel Trojman Thanks to ESPE
Similar presentations
