1. Lecture 1 - Introduction
ECE 5465 Chapter 1 of text
9/22/2010
Lecture 1 - Introduction

2. Lecture 1 - Introduction
Outline
Design abstraction
MU0
Instruction set design
9/22/2010
Lecture 1 - Introduction

3. Lecture 1 - Introduction
In the beginning ….
The dawn of the modern era started with the stored program computer …..
Much yet to be written
All stored program computers operate on the same core principals. The start of the execution of any instructions begins :
Mem(PC)  IR
9/22/2010
Lecture 1 - Introduction

4. Lecture 1 - Introduction
Modern design
All modern designs are done using design abstraction.
The abstraction level description ends up as transistors on an ic after translation by multiple CAD tools.
There are various dimension to abstraction.
The hardware dimension
The HDL dimension
The power dimension
9/22/2010
Lecture 1 - Introduction

5. Lecture 1 - Introduction
MU0
MU0 is much like MicroBaby, an accumulator architecture
MU0 instruction set is simpler than the MicroBaby instruction set. It only has Load, Store, Add, and Subtract, and two conditional jumps.
It has 16-bit data and address versus just the 8-bit of MicroBaby, so it has 64K bytes of main memory.
9/22/2010
Lecture 1 - Introduction

6. Lecture 1 - Introduction
MU0 Structure
The datapath and instructions
9/22/2010
Lecture 1 - Introduction

7. Lecture 1 - Introduction
MU0 datapath detail
A more detailed view of the architecture
9/22/2010
Lecture 1 - Introduction

8. The MU0 instruction bits
Instruction encoding – ref text
9/22/2010
Lecture 1 - Introduction

9. Instruction set design
Instruction set design involves choosing the binary encoding of each instruction
Best to choose one where the instruction word is broken into fields, with each field having a specific meaning or purpose.
Then, what goes into what happens on the busses during each cycle of execution.
Here we can further study MicroBaby and the timing of all the control signals.
9/22/2010
Lecture 1 - Introduction

10. Then RISC was discussed
The reference for the paper that started it all is given. (for RISC on page 24) “The Case for the Reduced Instruction Set Computer”
Core elements of “pure” RISC (see pg 24)
Fixed instruction size
Load/Store
Large Register Bank
RISC advantages
Small die size / shorter development time / higher performance
RISC drawbacks
Poor code density
No x86 compatibility – no IBM PC compatibility
ARMs answer for code density – the THUMB architecture
9/22/2010
Lecture 1 - Introduction

11. Lecture 1 - Introduction
9/22/2010
Lecture 1 - Introduction

12. Lecture 1 - Introduction
9/22/2010
Lecture 1 - Introduction

13. Lecture 1 - Introduction
9/22/2010
Lecture 1 - Introduction

14. Lecture 1 - Introduction
9/22/2010
Lecture 1 - Introduction

15. Lecture 1 - Introduction
9/22/2010
Lecture 1 - Introduction

16. Lecture 1 - Introduction
9/22/2010
Lecture 1 - Introduction