1. Design Technologies
Custom
Std Cell
Performance
Gate Array
FPGA
Cost

2. Views / Abstractions / Hierarchies
Structural
Behavioral
device
Circuit
Logic
Architectural
Physical
D.Gajski, Silicon Compilation, Addison Wesley, 1988

3. N-Channel Enhancement mode MOS FET
Four Terminal Device - substrate bias
The “self aligned gate” - key to CMOS

4. The MOS Transistor Digital Integrated Circuits © Prentice Hall 1995
Introduction

5. MOS transistors Types and Symbols
Digital Integrated Circuits
© Prentice Hall 1995
Introduction D D G G S S
NMOS
Enhancement
NMOS
Depletion D D G G B S S
NMOS with
PMOS
Enhancement
Bulk Contact

6. The Basic Idea…
Voltage on the Gate controls the current through the source/drain path
N-Channel - N-Switches are ON when the Gate is HIGH and OFF when the Gate is LOW
P-Channel - P-Switches are OFF when the Gate is HIGH and ON when the Gate is LOW
(ON == Circuit between Source and Drain)

7. Transistors as Switches
N Switch G S D 1
Passes “good zeros”
P Switch G S D 1
Passes “good ones”

8. ….The Rest of the Story...
Put them in series - both must be on to complete the circuit
Put them in parallel - either can be on to complete the circuit
Generate all sorts of Switching Functions
NOT the same as Boolean Functions.... Its RELAY logic - pin ball machines

9. Series Parallel StructuresD 1 G S D D 1 1 G G D S S 1 G S
N Channel: on=closed when gate is high

10. NMOS Transistors in Series/Parallel Connection
Digital Integrated Circuits
© Prentice Hall 1995
Introduction
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high

11. Series Parallel Structures(2)D G S D D G G D S S G S
P Channel: on=closed when gate is low

12. PMOS Transistors in Series/Parallel Connection
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

13. Series Parallel Structures (3)
N Switch G S D S 1
Passes “good zeros” G S D
Passes “good ones” S’ 1
P Switch
Open Circuit, High Z
Bi-directional Switch

14. From Switches to Boolean Functions...
Use the Switching Functions to provide paths to Vdd or GND
Vdd is the source of all Truth (Vdd = = 1)
GND is the source of all Falsehood (GND == 0)
P-channel
N-channel 1 1

15. The Inverter
True to False / False to True Converter
1/0
0/1

16. …That’s it!
This is Non-Trivial: it defines the basis for the logic abstraction which is essential for all Boolean functions.
Provide a path to VDD for 1
Provide a path to GND for 0
For complex functions - provide complex paths

17. Four Views
Logic Transistor Layout Physical

18. Cross-Section of CMOS Technology
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

19. Magic Layout of Inverter

20. Magic “Palette” of Layers

21. Modern Interconnect

22. Chain of Inverters A B C D E
Feedback loop

23. Which is which? A B C D E

24. CMOS logic structures Static (logic) structures
Complementary structures
Pass structures
Pseudo-NMOS structures
Dynamic (logic) structures
precharged
latched
combinations
Memory structures
static
quasi-static
dynamic
I/O structures

25. Complementary Structures
Big -- 2 x N transistors for N inputs
Use the “dual” for N and P chains
Can/should be sized for maximum speed/minimum power-area
Can use well known circuit minimization techniques
Fast
Low static power dissipation
Possibly high dynamic power dissipation

26. Static CMOS Circuit
Digital Integrated Circuits
© Prentice Hall 1995
Introduction
At every point in time (except during the switching
transients) each gate output is connected to either V DD or ss
via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the
dynamic
circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

27. Static CMOS Digital Integrated Circuits © Prentice Hall 1995
Introduction

28. Complementary CMOS Logic Style Construction (cont.)
Digital Integrated Circuits
© Prentice Hall 1995
Introduction

29. Example Gate: NAND Digital Integrated Circuits © Prentice Hall 1995
Introduction

30. Example Gate: NOR Digital Integrated Circuits © Prentice Hall 1995
Introduction