1. Systems Architecture I
September 4, 1997
Systems Architecture I (CS ) Lecture 12: Design of the MIPS ALU*
Jeremy R. Johnson
Mon. Nov. 13, 2000
*This lecture was derived from material in the text (sec ).
All figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).
Nov. 13, 2000
Systems Architecture I

2. Systems Architecture I
September 4, 1997
Introduction
Objective: To learn what operations are performed by the Arithmetic Logic Unit (ALU) and to learn how the MIPS ALU is implemented.
Topics
MIPS logical operations
Full Adder
1-But ALU
The design of the MIPS 32-Bit ALU
Overflow and Overflow Detection
Carry Lookahead
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Systems Architecture I

3. Addition and Subtraction
Carry-ripple adder
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Systems Architecture I

4. Systems Architecture I
Overflow Detection
Overflow occurs in the following situations
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Systems Architecture I

5. Systems Architecture I
Logical Operations
Shift left << sll
Shift right >> srl
Shift right arithmetic sra
Bitwise and & and, andi
Bitwise or | or, ori
Bitwise complement (not) ~ not (pseudo)
Exclusive or ^ xor, xori
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Systems Architecture I

6. Representation of Shift Instruction
September 4, 1997
Representation of Shift Instruction
Example
sll $t2, $s0, # $t2 = $s0 << 8
$t2 = $8, $s0 = $16
op rs rt rd shamt func
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Systems Architecture I

7. Example use of Logical Operations
Int data;
struct {
unsigned int ready: ;
unsigned int enable: ;
unsigned int receivedByte: 8;
} receiver; …
data = receiver.receivedByte;
receiver.ready = 0;
receiver.enable = 1;
Assume data in $s0
receiver in $s1
sll $s0, $s1, 22
srl $s0, $s0, 24
andi $s1, $s1, 0xfffe
ori $s1, $s1, 0x0002
| receivedByte | enable | ready
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Systems Architecture I

8. Systems Architecture I
Building Blocks
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Systems Architecture I

9. Systems Architecture I
Full Adder
Sum = parity(a,b,CarryIn)
a xor b xor c + abc  a xor b xor c
CarryOut = majority(a,b,CarryIn)
bCarryIn + aCarryIn + ab + abCarryIn 
bCarryIn + aCarryIn + ab b a
CarryIn
Sum
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Systems Architecture I

10. Systems Architecture I
One-Bit ALU
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Systems Architecture I

11. Systems Architecture I
Building a 32-Bit ALU
Chain 32 1-Bit ALUs
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Systems Architecture I

12. Supporting Subtraction
Subtraction is equivalent to adding the inverse
In two’s complement a + b + 1
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Systems Architecture I

13. Systems Architecture I
Overflow and SLT
Modify last 1-Bit ALU
SLT set if (a < b)  a - b < 0
Check sign bit after subtraction
Check overflow in last 1-Bit ALU
Need to take overflow into account for SLT
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Systems Architecture I

14. 32-Bit ALU with Sub and Slt
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Systems Architecture I

15. Systems Architecture I
Support Beq
a = b  a - b = 0
Zero = (Result31 +    + Result0)
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Systems Architecture I

16. Systems Architecture I
Final 32-Bit ALU
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Systems Architecture I

17. Systems Architecture I
Carry Lookahead Adder
if (ai-1 = bi-1) then ci = “kill”
if (ai-1 = bi-1) then ci = “generate”
if (ai-1  bi-1) then ci = ci “propagate” +
ai-1
bi-1
ci-1 ci
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Systems Architecture I

18. Systems Architecture I
Combined Carry Status
xi = kill if (ai-1 = bi-1)
xi = generate if (ai-1 = bi-1)
xi = propagate if (ai-1  bi-1)
yi = yi-1  xi = x1    xi
FAi-1
FAi
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Systems Architecture I

19. Calculating Carry from Carry Status
Lemma:
yi = kill  ci = 0
yi = generate  ci = 1
yi = propagate does not occur
Proof:
yi = kill  xi = kill  ci = 0 or
xi = propagate and yi-1 = kill and ci = majority(ci-1, ai, bi) = ci-1 = kill (by induction)
yi = generate  xi = generate  ci = 1 or
xi = propagate and yi-1 = generate and ci = majority(ci-1, ai, bi) = 1 (by induction)
yi = propagate  xi = propagate and yi-1 = propagate, which by induction leads to a contradiction
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Systems Architecture I

20. Systems Architecture I
Parallel Prefix
Fast (parallel computation of yi in log time)
x x x x x x x x7
[0,1] [1,2] [2,3] [3,4] [4,5] [5,6] [6,7]
[0,2] [0,3] [1,4] [2,5] [3,6] [4,7]
[0,0] [0,1] [0,2] [0,3] [0,4] [0,5] [0,6] [0,7]
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Systems Architecture I

21. Systems Architecture I
Parallel Prefix
Nov. 13, 2000
Systems Architecture I