1. Finite State Machines Experiment 4 Introduction
ECE 448 – FPGA and ASIC Design with VHDL
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University

2. Sequence detector
ECE 448 – FPGA and ASIC Design with VHDL

3. Our Example Non-resetting detector of the sequence: (10)+ (11) sc sbsa
Input:
Output:
ECE 448 – FPGA and ASIC Design with VHDL

4. Our Example Joystick left = ‘1’ Joystick right = ‘0’
ECE 448 – FPGA and ASIC Design with VHDL

5. Moore State Diagram
ECE 448 – FPGA and ASIC Design with VHDL

6. Moore Machine - ASM Chart
ECE 448 – FPGA and ASIC Design with VHDL

7. Mealy State Diagram
ECE 448 – FPGA and ASIC Design with VHDL

8. Mealy Machine - ASM Chart
ECE 448 – FPGA and ASIC Design with VHDL

9. Questions?
ECE 448 – FPGA and ASIC Design with VHDL