1. SVT detector electronics
Mauro Villa - INFN & Università di Bologna
Overview:
- SuperB SVT
- Layer 0 peculiarities
- SVT channels and reading chains
- Rate, links and event size
- SVT in trigger schema

2. SuperB SVT
40 cm
30 cm
20 cm
Layer0
Layer Radius cm cm cm cm
to 12.7 cm
to 14.6 cm
Baseline: use an SVT similar to the BaBar one adding a Layer 0
Layer 0 options: double layer thin MAPS pixels, striplets (double sided), single layer hybrid pixel. Load to DAQ calculated for MAPS double layer.
Each layer has several modules, mechanically independent units (52+8)
Each module has 2 half-modules, electrically independent units:
Sensor, front-end chips, HDI with power/signal input and data output link
Pixel half-module
Strip(lets) half-module
Data
Pixel sensor +
front-end chips
HDI
Power/Signal
HDI
Si Wafers
Data
Power/Signal
Front-end chips
Frascati, 2/12/09

3. Layer0 peculiarities MAPS Pixel sensors (40 um pitch)
Rad hard environment
Large machine background ( 15 mm from beam line)
Fundamental the first point of a track for vertexing
MAPS Pixel sensors (40 um pitch)
Apsel6D – or similar
320x216 pixels a 40 um pitch.
Active Area = 110 mm2
Completely data driven architecture
Space time coordinates
Time granularity down to 100 ns
from us
Time ordered hits
External Time stamp clock.
Hit rate expected: 110 Mhit/s/chip
(with a safety factor>5).
Frascati, 2/12/09

4. SuperB Layer 0 MAPS Module
6 Chips: 1.1 cm^2 Signal lines: 180 in 1 cm width
Hit Rate: 110 MHz/chip (safety>5)
Module Rates: 660 MHz
Bandwidth: 20 Gbit/s (design parameters)
Thin aluminium bus for power and signals
Main technological challenge:
Line spacing (<100 um)
Frequency (> 100 MHz)
Frascati, 2/12/09

5. SuperB SVT in numbers 6 layers: Layer0 + 5 layers like BaBar SVT Layer
Modules
HDI
ReadOut
Section (ROS)
chips/ROS
chips
channels
0- Pixels 8 16 32 6
192
13.1E+06 1 12 24
7-8
180
23.0E+03 2
7-10
204
26.1E+03 3
10-14
288
36.9E+03 4 64
4-11
480
61.4E+03 5 18 36 72
4-14
648
82.9E+03
total 60
120
240
2052
13.4E+06
Frascati, 2/12/09

6. Bkgd Hit Rate (MHz/cm^2)
Present values … might change! L0 L1 L2 L3 L4 L5
Frascati, 2/12/09

7. General DAQ framework
Frascati, 2/12/09

8. DAQ reading chain for L0
HDI with line drivers, copper cables, Rad-hard ram+L1 handling logic, optical links
RAM and
L1 logic
Copper
Link
Buffers and
line drivers
Optical 1Gbit/s
Optical Link
2.5 Gbit/s
FEB
ROM
Transition card
Near detector
“soft” rad area
Off detector
low rad area
Counting room
Std electronics
On detector
High rad area
Design limited by the large data rate on L0: 16 Gbit/s/ROS
and the link bandwidth (1 Gbit/s/link)
Simplicity: 1 ROS to 1 FEB
32 x1Gb/s links;
Frascati, 2/12/09

9. DAQ reading chain for L1-L5
Full data shipment to FEBs; 1 FEB serves max 12 ROS;
optical 1Gbit/s
Links
Line drivers
Optical Link
2.5 Gbit/s
HDI
Si Wafers
Data
Power/Signal
Front-end chips
FEB
ROM
Transition card
Near detector
“soft” rad area
On detector
High rad area
Off detector
low rad area
Counting room
Std electronics
Max 3 Gbit/s/ROS on L1, L2; Gbit/s/ROS on L3-L5
Grouping: up to 12 ROS to 1 FEB
Resources: 252x 1Gbit/s links, 24 FEBs, 24x2.5Gbit/s links
Frascati, 2/12/09

10. Rates, links & event size
Trigger rate: 150 kHz, SVT readout window: 396 ns
Layer
1Gbit/s links
FE Boards
2 Gbit/s DAQ links
To ROM
DAQ rate/FEB
(Gbit/s) (*)
Triggered event size (kB/ev)
0- Pixels
32 (*) 32
1.2 26 1 72 6
0.8
3.2 2
0.6
3.6 3 48 4
1.6 24
0.4
1.0 5 36
0.5
1.3
total
284 56
(*) Triggered data only
Frascati, 2/12/09

11. SVT in trigger schema Purposes/Advantages
Thanks to the data-push architecture of FSSR, L1-L5 will be read out continuously
L3-L5 could be used for online-track finding
Purposes/Advantages
Early (<2µs) identification of interesting events
L1 triggering
Background track identification
tracks not coming from primary vertex region
Bhabha veto (?)
Back to back in r-phi
Quick track finding might speed-up downstream processing
Seeded track finding; reduction of reconstruction farm
Many ideas, many possibilities, but no systematic study yet
Frascati, 2/12/09

12. Conclusions and main numbers
Full SVT readout with 56 Front-End Boards
56 DAQ links, 56 ECS, 56 FTCS
Large use of 1 Gbit/s Optical links (284 in total)
Moderate use of DAQ links (2 Gbit/s) assuming suitable ROS data grouping
SVT Time-tagging of events every 132 ns; Events span a time range of 3x132 ns=396 ns.
Event size: 36 kB (with a safety factor of 5 on background rate at L0)
Possibility for early (<2µs) track finding for L1 applications or seeded reconstruction at HLTs
Frascati, 2/12/09