1. ENEE 303 7th Discussion

2. Contents
Logic gate
Homework 6 problem 2

3. Logic Inverter (logic “1”) (logic “1”) VIH VOH VOL VIL (logic “0”)
ENEE 303 Fall 2017

4. Voltage Transfer Characteristic (VTC) of an Inverter
transition region between 𝒗 𝑰 = 𝑽 𝑰𝑳 to 𝒗 𝑰 = 𝑽 𝑰𝑯
(logic “1”)
𝒗 𝒐 = 𝑽 𝑶𝑯 for 𝒗 𝑰 ≤ 𝑽 𝑰𝑳
𝒗 𝒐 = 𝑽 𝑶𝑳 for 𝒗 𝑰 ≥ 𝑽 𝑰𝑯
(logic “0”)
ENEE 303 Fall 2017

5. Noise Margins of an Inverter
𝒗 𝑰𝟐 = 𝒗 𝑶𝟏 + 𝒗 𝑵
For 𝒗 𝑶𝟏 = 𝑽 𝑶𝑳 , 𝑽 𝑶𝑳 + 𝒗 𝑵 ≤ 𝑽 𝑰𝑳
𝑵𝑴 𝑳 = 𝑽 𝑰𝑳 − 𝑽 𝑶𝑳
For 𝒗 𝑶𝟏 = 𝑽 𝑶𝑯 , 𝑽 𝑶𝑯 + 𝒗 𝑵 ≤ 𝑽 𝑰𝑯
𝑵𝑴 𝑯 = 𝑽 𝑶𝑯 − 𝑽 𝑰𝑯
ENEE 303 Fall 2017

6. Characteristics of an Ideal Inverter
𝑽 𝑶𝑯 = 𝑽 𝑫𝑫
𝑽 𝑶𝑳 =𝟎
𝑽 𝑰𝑳 = 𝑽 𝑰𝑯 = 𝑽 𝑴 = 𝑽 𝑫𝑫 𝟐
𝑵𝑴 𝑳 = 𝑵𝑴 𝑯 = 𝑽 𝑫𝑫 𝟐
ENEE 303 Fall 2017

7. The CMOS Inverter
ENEE 303 Fall 2017

8. VTC of the CMOS Inverter with Matched 𝑸 𝑵 and 𝑸 𝑷
𝒊 𝑫𝑷 = 𝒊 𝑫𝑵
For QN,
for 𝒗 𝒐 ≥ 𝒗 𝑰 − 𝑽 𝒕𝒏 (saturation)
𝒊 𝑫𝑵 = 𝟏 𝟐 𝒌 𝒏 ′ 𝑾 𝑳 𝒏 𝒗 𝑰 − 𝑽 𝒕𝒏 𝟐
for 𝒗 𝒐 < 𝒗 𝑰 − 𝑽 𝒕𝒏 (triode)
𝒊 𝑫𝑵 = 𝒌 𝒏 ′ 𝑾 𝑳 𝒏 𝒗 𝑰 − 𝑽 𝒕𝒏 𝒗 𝒐 − 𝟏 𝟐 𝒗 𝒐 𝟐
NML = VIL - VOL; NMH = VOH - VIH
For QP,
for 𝒗 𝒐 ≥ 𝒗 𝑰 + 𝑽 𝒕𝒑 (saturation)
𝒊 𝑫𝑵 = 𝟏 𝟐 𝒌 𝒑 ′ 𝑾 𝑳 𝒑 𝑽 𝑫𝑫 − 𝒗 𝑰 − 𝑽 𝒕𝒑 𝟐
for 𝒗 𝒐 < 𝒗 𝑰 + 𝑽 𝒕𝒏 (triode)
𝒊 𝑫𝑷 = 𝒌 𝒑 ′ 𝑾 𝑳 𝒑 𝑽 𝑫𝑫 − 𝒗 𝑰 − 𝑽 𝒕𝒑 𝑽 𝑫𝑫 − 𝒗 𝒐 − 𝟏 𝟐 𝑽 𝑫𝑫 − 𝒗 𝒐 𝟐
ENEE 303 Fall 2017

9. Example
Consider a CMOS inverter fabricated in a 0.18-mm process for which 𝑉 𝐷𝐷 =1.8 V, 𝑉 𝑡𝑛 = 𝑉 𝑡𝑝 =0.5 V, 𝜇 𝑛 =4 𝜇 𝑝 , and 𝜇 𝑛 𝐶 𝑜𝑥 =300 μA V 2 . In addition, 𝑄 𝑛 and 𝑄 𝑝 have 𝐿=0.18 μm and 𝑊 𝐿 𝑛 =1.5.
Find 𝑊 𝑝 that results in 𝑉 𝑀 = 𝑉 𝐷𝐷 2=0.9 V . What is the silicon area utilized by the inverter in this case?
To design the CMOS inverter 𝑉 𝑀 = 𝑉 𝐷𝐷 2=0.9 V , the MOSFETs must be matched.
𝑘 𝑛 ′ 𝑊 𝐿 𝑛 = 𝑘 𝑝 ′ 𝑊 𝐿 𝑝 ⇒ 𝑊 𝑝 𝑊 𝐿 = 𝜇 𝑛 𝜇 𝑝 ⇒ 𝑊 𝑝 =1.08 𝜇m
ENEE 303 Fall 2017

10. Example
(b) For the matched case in (a), find the values of 𝑉 𝑂𝐻 , 𝑉 𝑂𝐿 , 𝑉 𝐼𝐻 , 𝑉 𝐼𝐿 , and the noise margins 𝑁𝑀 𝐿 and 𝑁𝑀 𝐻 . For 𝑣 𝐼 = 𝑉 𝐼𝐻 , what value of 𝑣 𝑜 results? This can be considered the worst-case value of 𝑉 𝑂𝐿 . Similarly, for 𝑣 𝐼 = 𝑉 𝐼𝐿 , find 𝑣 𝑜 that is the worst-case value of 𝑉 𝑂𝐻 . Now, use these worst-case values to determine more conservative values for the noise margins.
𝑉 𝑂𝐻 = 𝑉 𝐷𝐷 =1.8 V
𝑉 𝑂𝐿 =0 V
𝑉 𝐼𝐻 = 𝑉 𝐷𝐷 −2 𝑉 𝑡 =1 V
𝑉 𝐼𝐿 = 𝑉 𝐷𝐷 +2 𝑉 𝑡 =0.8 V
𝑁𝑀 𝐻 = 𝑉 𝑂𝐻 − 𝑉 𝐼𝐻 =0.8 V
𝑁𝑀 𝐿 = 𝑉 𝐼𝐿 − 𝑉 𝑂𝐿 =0.8 V
Note that the noise margins are close to ideal value of 0.9 V!!
ENEE 303 Fall 2017

11. Example
(b) For the matched case in (a), find the values of 𝑉 𝑂𝐻 , 𝑉 𝑂𝐿 , 𝑉 𝐼𝐻 , 𝑉 𝐼𝐿 , and the noise margins 𝑁𝑀 𝐿 and 𝑁𝑀 𝐻 . For 𝑣 𝐼 = 𝑉 𝐼𝐻 , what value of 𝑣 𝑜 results? This can be considered the worst-case value of 𝑉 𝑂𝐿 . Similarly, for 𝑣 𝐼 = 𝑉 𝐼𝐿 , find 𝑣 𝑜 that is the worst-case value of 𝑉 𝑂𝐻 . Now, use these worst-case values to determine more conservative values for the noise margins.
For 𝑣 𝐼 = 𝑉 𝐼𝐻 ,
𝑣 𝑂 = 𝑉 𝐼𝐻 − 𝑉 𝐷𝐷 2 =0.1 V= 𝑉 𝑂𝐿,𝑚𝑎𝑥
𝑁𝑀 𝐿 = 𝑉 𝐼𝐿 − 𝑉 𝑂𝐿,𝑚𝑎𝑥 =0.7 V
For 𝑣 𝐼 = 𝑉 𝐼𝐿 ,
𝑣 𝑂 = 𝑉 𝐷𝐷 −0.1=1.7 V= 𝑉 𝑂𝐻,𝑚𝑖𝑛
𝑁𝑀 𝐻 = 𝑉 𝑂𝐻,𝑚𝑖𝑛 − 𝑉 𝐼𝐻 =0.7 V
ENEE 303 Fall 2017

12. Example
(c) For the matched case in (a), find the output resistance of the inverter in each of its two states.
𝑟 𝐷𝑆𝑁 = 1 𝜇 𝑛 𝐶 𝑜𝑥 𝑊 𝐿 𝑛 𝑉 𝐷𝐷 − 𝑉 𝑡𝑛 =1.71 kΩ= 𝑟 𝐷𝑆𝑃
(d) If 𝜆 𝑛 = 𝜆 𝑝 =0.2 V −1 , what is the inverter gain at 𝑣 𝐼 = 𝑉 𝑀 . If a straight line is drawn through the point 𝑣 𝐼 = 𝑣 𝑜 = 𝑉 𝑀 with a slope equal to the gain, at what values of 𝑣 𝐼 does it intercept the horizontal lines 𝑣 𝑜 =0 and 𝑣 𝑜 = 𝑉 𝐷𝐷 ? Use these intercepts to estimate the width of the transition region of the VTC.
With the inverter biased at 𝑣 𝐼 = 𝑣 𝑜 = 𝑉 𝑀 =0.9 V, both MOSFETs will operate at 𝑉 𝑂𝑉 = 𝑉 𝑀 − 𝑉 𝑡 =0.4 V. This yields 𝐼 𝐷 =36 𝜇A.
ENEE 303 Fall 2017

13. Example (d) Then, the transconductance parameters of both MOSFETs is
𝑔 𝑚𝑛 = 𝑔 𝑚𝑝 = 2 𝐼 𝐷 𝑉 𝑂𝑉 =0.18 mA 𝑉 2
Their output resistances are also the same,
𝑟 𝑜𝑛 = 𝑟 𝑜𝑝 = 1 𝜆 𝐼 𝐷 =139 kΩ
The gain at the midpoint is,
𝐴 𝑣 =− 𝑔 𝑚𝑛 + 𝑔 𝑚𝑝 𝑟 𝑜𝑛 ∥ 𝑟 𝑜𝑝 =−25 V 𝑉
The width of the transition region is then,
∆𝑉= − 0.9− =0.072 V
ENEE 303 Fall 2017

14. Basic Structure of CMOS Logic-Gate Circuits
PUN conducts when the input combinations yield Y = 1
PUN circuit consists of PMOS transistors
PDN conducts when the input combinations yield Y = 0
PDN circuit consists of NMOS transistors
ENEE 303 Fall 2017

15. Examples of Pull-Up Networks
ENEE 303 Fall 2017

16. Examples of Pull-Down Networks
ENEE 303 Fall 2017

17. Usual and Alternative Circuit Symbols for MOSFETs
ENEE 303 Fall 2017

18. A Two-Input CMOS NOR Gate
ENEE 303 Fall 2017

19. A Two-Input CMOS NAND Gate
ENEE 303 Fall 2017

20. CMOS Realization of a Complex Gate
ENEE 303 Fall 2017

21. Designing CMOS Logic Circuits
ENEE 303 Fall 2017