1. Chapter 6 – Part 4 SYEN 3330 Digital Systems SYEN 3330 Digital Systems
Dr. Anthony DeGregoria and I would like to thank WIN Foundation and the Wisconsin Venture Network for the opportunity present to you today.
SYEN 3330 Digital Systems

2. Overview of Chapter 6 Types of Sequential Circuits Storage Elements
Latches
Flip-Flops
Sequential Circuit Analysis
State Tables
State Diagrams
Sequential Circuit Design
Specification
Assignment of State Codes
Implementation
HDL Representation
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3. Developing the State Diagram
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4. Developing the State Diagram
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5. Sequence Recognizer Procedure
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6. Sequence Recognizer Example
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7. Example: Recognize 1101
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8. Recognize 1101 (Continued)
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9. Recognize 1101 (Continued)
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10. Recognize 1101 (Continued)
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11. Complete the Diagram (1101)
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12. Add Missing Arcs
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13. 1101 State Table from Diagram
From State A, the “0” and “1” input transitions have been filled in along with the outputs.
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14. Complete 1101 State Table
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15. Moore Model for 1101
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16. Moore Diagram for 1101
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17. Moore State Table for 1101
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18. Second State Diagram Example
A register consists of an ordered set of n flip-flops plus combinational logic to determine its next state.
If a register can be designed as a set of n identical cells, the register cell can be designed as a two-state sequential circuit.
Next we will consider such as example.
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19. Parallel Load Register with Synchronous Clear and Load
Register Specification
Diagram:
Table:
CLS
LDS
CLK
Data_in (7:0)
Data_out(7:0)
Register(7:0)
RESET
(Async)
Operation
CLS
LDS
Result (Next State)
Hold Reg
Data_out
Load Reg 1
Data_in
Clear Reg -
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20. Second Example: Register Cell Design
By definition, a register cell is a sequential circuit that:
contains one flip-flop (2 states)
has the flip-flop output as the primary external register output (Moore model)
Cell Diagram:
CLS
LDS
CLK
Data_in (i)
Data_out(i)
Reg. Cell(i)
RESET
(Async) FF
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21. Second Example: State Diagram Design
Initial State:
Add Load:
Add Clear:
A/0
RESET
1, 0
State/Data_out(i)
LDS,Data_in
1, 1
A/0
RESET
B/1
1, 0
1, 1
0, 1, 0; 1, -, -
State/Data_out(i)
CLS,LDS,Data_in
0, 1, 1
RESET
A/0
B/1
0,1,0; 1,-,-
0,1,1
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22. Second Example: State Diagram Design
Make the state unchanged (Hold Reg) by adding all unused input combinations for each state.
CLS,LDS,Data_in
State/Data_out(i)
0, 1, 0; 1, -, -
0, 1, 1
RESET
A/0
B/1
0,1,0; 1,-,-; 0,0,-
0,1,1; 0,0,-
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23. Second Example: State Table
From State Diagram: CLS, LDS, Data_in
Input:
State:
000
001
010
011
100
101
110
111
Output A B 1
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