1. Digital Logic & Design
Dr. Waseem Ikram
Lecture No. 31

2. Recap Digital Clock Frequency Counter
Divide by 60 counter timing diagram
Hours Counter circuit
Hours Counter timing diagram
Frequency Counter
Sampling intervals
Detailed Circuit diagram
Timing diagram

3. Next-State Table for a 3-bit Up-Counter
Present State
Next State Q2 Q1 Q0 1

4. J-K flip-flop Transition table
Flip-flop Inputs
Output Transitions J K Qt
Qt+1 x 1

5. J-K flip-flop input table
Present State
Next State
J-K flip-flop inputs Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 1 x

6. Karnaugh Map for J2 and K2 inputs
Q2Q1/Q0 1 00 01 11 x 10
Q2Q1/Q0 1 00 01 11 x 10

7. Karnaugh Map for J1 and K1 inputs
Q2Q1/Q0 1 00 01 x X 11 10
Q2Q1/Q0 1 00 x 01 11 10

8. Karnaugh Map for J0 and K0 inputs
Q2Q1/Q0 1 00 x 01 11 10
Q2Q1/Q0 1 00 x 01 11 10

9. Implementation of the Sequential Circuit

10. S-R flip-flop Transition table
Flip-flop Inputs
Output Transitions S R Qt
Qt+1 x 1

11. S-R flip-flop input table
Present State
Next State
S-R flip-flop inputs Q2 Q1 Q0 S2 R2 S1 R1 S0 R0 1 x

12. Karnaugh Map for S2 and R2 inputs
Q2Q1/Q0 1 00 01 11 x 10
Q2Q1/Q0 1 00 01 11 x 10

13. Karnaugh Map for S1 and R1 inputs
Q2Q1/Q0 1 00 01 x 11 10
Q2Q1/Q0 1 00 x 01 11 10

14. Karnaugh Map for S0 and R0 inputs
Q2Q1/Q0 1 00 01 11 10
Q2Q1/Q0 1 00 01 11 10

15. S-R flip-flop based implementation of 3-bit Synchronous Counter

16. Timing diagram of the S-R flip-flop based 3-bit Synchronous Counter

17. Recap
Clocked Sequential circuits
State diagram

18. Design of Sync. Counters
Next-State table (tab 1)
Flip-flop transition table (tab 2)
Flip-flop input table (tab 3)
Karnaugh maps (tab 4)
Logical expressions for flip-flop inputs
Sequential circuit Implementation (fig 1)

19. Design of S-R Sync. Counters
Flip-flop transition table (tab 5)
Flip-flop input table (tab 6)
Karnaugh maps (tab 7)
Logical expressions for flip-flop inputs
Sequential circuit Implementation (fig 2a)
Timing diagram (fig 2b)