1. CPLD Product Applications
XC9500XL Architecture
CPLD Product Applications
95XLarch 1

2. This is the XC9500XL FastFLASH CPLD Technical Seminar
Welcome!
This is the XC9500XL FastFLASH CPLD Technical Seminar
Xilinx

3. Agenda Architecture ISP Electrical Compatibility Timing
This presentation consists of about an hour worth of material spread out over the following 8 categories:
(read above)
If you have used the X9500 family, please pay attention to some of the small details that can really make a difference in both speed as well as design density.
If the XC9500 and XC9500XL are new to you, please don’t hesitate to ask questions on any of the topics discussed, at the appropriate time.
We will also handle questions at the conclusion.

4. High Level Architecture
(Spend as much time here as needed. Ask for questions:)
Start at the left, work to the right, then go up to the JTAG/ISP controller. For instance:
All signals enter & exit at the I/O pins, which are attached to the JTAG scan chain. From there, software directs them appropriately thru FastCONNECT 2, a dense switch matrix. Parcels of up to 54 signals can be assigned to each Function Block - similar to a PAL - to perform logic. The resulting functions pass back to the I/O pins or visit other FBs, as needed.
Note that I/O pins can be sacrificed to be global clocks, tristates or set/reset signals, as chosen. All are fundamentally the same.
The JTAG controller holds the TAP controller and also passes ISP instructions to the ISP controller. The ISP controller is where the charge pumps and programming circuitry live. Literally a programmer on each chip!

5. Function Block 18 Macrocells per Function Block 18 Macrocell Feedbacks
2 or 4
I/O 18
Product-
Term
Allocators
AND
Array
Global
Tri-State
Clocks
18 I/O
signals
18 Macrocells
per Function
Block 3 54
From
FastCONNECT II
18 Macrocell Feedbacks To
FastCONNECT II

6. Macrocell
XC9500XL Macrocell strongly resembles the XC9500 one. The primary differences are simply the option of inverting the chosen clock at each macrocell, and the inclusion of a product term driven clock enable. Other than that they are very similar.
For the new user, this means the flops have the option of being bypassed, configured as D or T. Product term or global set/resets can be chosen at each macrocell. Likewise with global/p-term clocks and global/p-term tri-states.
In the rest state, there 5 p-terms associated with each macrocell. Each p-term has a local specialty function (p-term clock, p-term tri-state, etc), can participate in the local logic function, or be available to export to either neighboring macrocell. The software manages the configuration. If all of the specialty functions are used for a macrocell, it can get additional p-terms from neighboring macrocells at a small cascade time delay penalty.
It is possible, to forward all product terms (up to 90) within a FB into a single macrocell, if need be. This seldom occurs, but is architecturally possible.

7. Macrocell Five product terms are associated with each macrocell
Product terms can be used to generate OE, Reset, Set, CE, and Clock
Three global clocks and one global set/reset associated with each macrocell
D/T-type Register
Product terms can be borrowed from other macrocells

8. Product Term Allocator

9. Timing
This is the general timing model for XC9500XL parts. The model is the same for all family members. There are incremental timing parameters for each functional feature used that delays the signal. A full timing report for a design will be done - as a text file - in terms of the parameters indicated in the diagram, as well as in terms of some composite parameters. tPD is one such composite parameter and fMAX is another. Others are described in the data sheets and application notes.
From a practical viewpoint, additional timing information is provided in the Designing for High Speed XC9500XL application note.

10. Timing Example 1 tOUT tIN tPDI + tLOGI tPD = tIN + tPDI + tLOGI + tOUT
Function Block
tOUT
tIN
tPDI + tLOGI
This is probably the simples example of a composite timing parameter, tPD. Here we see the pin to pin propagation delay is the sum of the input buffer time, the internal tPD (connection), the transition across the logic and the output buffer time delay. As a rule, we specify the worst case max numbers at this point in time. This is pessimistic enough to guarantee the calculated timing is met when driving the specified external load.
tPD = tIN + tPDI + tLOGI + tOUT

11. Timing Example 2 tIN tPTA A tOUT B tLOGI + tPDI
Function Block A
tPTA
tOUT B
This simple extension of the previous example merely adds in one level of cascade time - tPTA - to the previous example, to show how the cascade chain derates the baseline performance. This covers one cascade time, as more are added, the number increases - by less than a nanosecond per cascade level.
tLOGI + tPDI
t A-> B = tIN + tPTA + tLOGI + tPDI + tOUT

12. Timing Example 3 tGCK tHI tSUI tSU = tIN + tLOGI + tSUI - tGCKQ
D/T
tGCK
tHI
tSUI
GCK
Adding flip flops does increase the complexity of describing the time behavior of a circuit. Here, we must include the calculations for setup, clock to out and hold time appropriately. The complexity increases dramatically, so it is appropriate that the design software create detailed timing reports that both summarize and detail the entire timing picture.
More examples are described in detail in an XC9500XL Timing Application note available in early October on the Xilinx WWW.
tSU = tIN + tLOGI + tSUI - tGCK
tCO = tGCK + tCOI + tOUT
tH = tGCK + tHI - tIN - tLOGI

13. XC9500XL Family
This table summarizes the capacity, speeds and packages for the XC9500XL family. It should be noted that not all packages line up with an identical XC9500 package, but where both exist, they are pin compatible.
I always remind people that you should always target designs for the slowest speed grade and lowest density for any package. In that manner, designs can be migrated to both faster and denser solutions as needed. This approach also guarantees the cheapest initial solution is the target.

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